Configurable Rx Elastic Buffer And Phase Alignment; Overview - Xilinx Virtex-5 RocketIO GTP User Manual

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Configurable RX Elastic Buffer and Phase Alignment

Overview

The GTP RX datapath has two internal parallel clock domains used in the PCS: the PMA
parallel clock domain (XCLK) and the RXUSRCLK domain. To receive data, the PMA
parallel rate must be sufficiently close to the RXUSRCLK rate, and all phase differences
between the two domains must be resolved.
domains, XCLK and RXUSRCLK.
RX Serial Clock
RX RX
SIPO
EQ CDR
PMA
PLL
Divider
From PMA PLL
RX-PMA
The GTP transceiver includes an RX elastic buffer to resolve differences between the
PMACLK and RXUSRCLK domain. The phase of the two domains can also be matched by
using the recovered clock from the transceiver to drive RXUSRCLK and adjusting its phase
to match XCLK. All RX datapaths must use one of these approaches. The costs and benefits
of each approach are shown in
Table 7-26: Buffering vs. Phase Alignment
Can use recovered clock or local clock (with
Clocking Options
clock correction)
Works immediately
Initialization
Buffer latency depends on features used (clock
Latency
correction and channel bonding)
Clock Correction/ Required for clock correction/channel
Channel Bonding bonding
Internal Data Width Can be 8 or 10 bits wide
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
PMA Parallel Clock
(XCLK)
Comma
Over- Detect
Polarity
Sampling
PRBS
Check
RX-PCS
Figure 7-20: Receiver Parallel Clock Domains
RX Buffer
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Configurable RX Elastic Buffer and Phase Alignment
Figure 7-20
10B
/
&
8B
Align
Loss of Sync
RX Status Control
RX Pipe Control
Table 7-26.
Must use recovered clock
Must wait for all clocks to stabilize then
perform alignment procedure
Lower latency than using the RX buffer
Must be 10 bits wide
shows the two parallel clock
PCS Parallel RX Interface
Clock Parallel Clock
(RXUSRCLK) (RXUSRCLK2)
Elastic
Buffer
FPGA
Logic
UG196_c7_20_102306
RX Phase Alignment
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