Txoutclk Driving Gtp Tx In 2-Byte Mode - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 6: GTP Transmitter (TX)

TXOUTCLK Driving GTP TX in 2-Byte Mode

The examples in
these cases, TXOUTCLK drives TXUSRCLK, and TXOUTCLK is divided by two using a
DCM or PLL to drive TXUSRCLK2.
94
GTP
Transceiver
Notes:
1. Refer to the Virtex-5 Data Sheet and the Virtex-5 Configuration Guide for
the maximum clock frequency and jitter limitations of BUFR.
Figure 6-4: TXOUTCLK Drives TXUSRCLK and TXUSRCLK2
Figure 6-5 and
PLLLKDET
TXOUTCLK
BUFG
GTP
TXUSRCLK2
Transceiver
TXUSRCLK
TXDATA (16 or 20 bits)
Figure 6-5: DCM Provides Clocks for 2-Byte Datapath
www.xilinx.com
TXOUTCLK
TXDATA
8 or 10 Bits
TXUSRCLK
TXUSRCLK2
Figure 6-6 use 2-byte datapaths (TXDATAWIDTH = 1). In
DCM
CLKFB CLK0
RST
CLKDV
CLKIN
LOCKED
Virtex-5 RocketIO GTP Transceiver User Guide
BUFG or
(1)
BUFR
UG196_c6_04_100406
Design In
FPGA
UG196_c6_05_051507
UG196 (v1.3) May 25, 2007
R