Clock Correction Options; Monitoring Clock Correction - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 7: GTP Receiver (RX)
Some protocols use clock correction sequences with don't care subsequences. The clock
correction circuit can be programmed to recognize these sequences using
CLK_COR_SEQ_1_ENABLE and CLK_COR_SEQ_2_ENABLE. When the enable bit for a
sequence is Low, that byte is independent from the value, always a match.
shows the mapping between the clock correction sequences and the clock correction
sequence enable bits.

Clock Correction Options

Use CLK_COR_REPEAT_WAIT to control the clock correction frequency. Set this value to
the minimum number of RXUSRCLK cycles required between clock correction events. Set
this attribute to zero to allow clock correction to occur any time.
Some protocols allow clock correction to occur at any time, but require that if the clock
correction circuit removes sequences, it should leave at least one sequence in the stream.
For protocols with this requirement, set CLK_COR_KEEP_IDLE to TRUE.

Monitoring Clock Correction

The clock correction circuit can be monitored using the RXCLKCORCNT and
RXBUFSTATUS ports. The RXCLKCORCNT entry in
values of RXCLKCORCNT to determine the status of the clock correction circuit. The
RXBUFSTATUS entry in
determine how full the RX elastic buffer is.
In addition to RXCLKCORCNT and RXBUFSTATUS, the RXRUNDISP signal can be taken
from the 8B/10B decoder interface (see
used to indicate when the RXDATA is the first byte of a clock correction sequence that was
replicated and added to the RX elastic buffer. To use the RXRUNDISP port to indicate
inserted idles instead of the current RX running disparity, set
CLK_COR_INSERT_IDLE_FLAG to TRUE.
174
CLK_COR_SEQ_x_y
Figure 7-26: Clock Correction Subsequence Settings with
RX_DECODE_SEQ_MATCH = TRUE
CLK_COR_SEQ_x_4 CLK_COR_SEQ_x_3
CLK_COR_SEQ_x_ENABLE
Figure 7-27: Clock Correction Sequence Mapping
Table 7-30
www.xilinx.com
9 8 7:0
8-Bit Clock Correction Sequence
1 = Sequence is a K Character
0 = Sequence is Regular Character
1 = Sequence Uses Inverted Disparity
0 = Sequence Uses Regular Disparity
CLK_COR_SEQ_x_2
4 3 2 1
Table 7-30
shows how to decode the values of RXBUFSTATUS to
"Configurable 8B/10B Decoder," page
Virtex-5 RocketIO GTP Transceiver User Guide
UG196_c7_23_092606
Figure 7-27
CLK_COR_SEQ_x_1
UG196_c7_24_092606
shows how to decode the
157) and
UG196 (v1.3) May 25, 2007
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