Configuring Shared Pll For Pci Express - Xilinx Virtex-5 RocketIO GTP User Manual

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7.

Configuring Shared PLL for PCI Express

This example shows how to set the shared PLL divider settings for PCI Express using
Equation
example is provided only to illustrate the process with
Use
1.
2.
3.
4.
5.
6.
7.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Select the PLL divider values
Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 2 and PLL_DIVSEL_REF = 1 results in a ratio of two.
5-1. The RocketIO GTP Wizard and
Equation 5-1 as described in the following steps:
Determine the required line rates.
For PCI Express, both TX and RX use a line rate of 2.5 Gb/s.
Determine the internal datapath width.
Because PCI Express uses 8B/10B encoding, an internal datapath width of 10 bits is
required.
Determine the desired reference clock rate.
This example uses a reference clock running at 100 MHz.
Calculate the required PLL clock rate.
Because the SIPO block uses both edges of the clock to deserialize data, it must be fed
a clock running at 2.5/2 = 1.25 GHz. Because this RX rate of 1.25 GHz is within the
operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be one.
The PLL clock rate is thus 1.25 x 1 = 1.25 GHz.
Calculate the required DIV value
Because the internal datapath with must be 10 bits and INTDATAWIDTH = 1, DIV = 5.
Calculate the required PLL divider ratio
Using the values f , DIV, and f
CLKIN
Equation 5-1 to calculate the divider ratio as shown in
ratio of 2.5.
PLL_DIVSEL_FB
---------------------------------------------------- -
PLL_DIVSEL_REF
Select the PLL divider values
Select the smallest divider values that result in the required PLL divider ratio. In this
case, using PLL_DIVSEL_FB = 5 and PLL_DIVSEL_REF = 2 results in a ratio of 2.5.
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Table 5-3 are simpler alternatives. This
Equation
determined above, rearrange
PLL_CLOCK
f
1.25 GHz
PLL_Clock
---------------------------------- - --------------------------------- -
= =
×
f DIV 100 MHz
CLKIN
Shared PMA PLL
5-1.
Equation 5-5. The result is a
2.5 Equation 5-5
=
×
5
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