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Xilinx VC7203 User Manual

Xilinx VC7203 User Manual

Virtex-7 fpga gtx transceiver characterization board
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VC7203 Virtex-7 FPGA
GTX Transceiver
Characterization Board
User Guide
UG957 (v1.0) October 10, 2012

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Summary of Contents for Xilinx VC7203

  • Page 1 VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board User Guide UG957 (v1.0) October 10, 2012...

  • Page 2: Revision History

    Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance;...

  • Page 3: Table Of Contents

    ............. 2 Chapter 1: VC7203 Board Features and Operation FPGA Compatibility .
  • Page 4 ..............64 www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...

  • Page 5: Chapter 1: Vc7203 Board Features And Operation

    (BOM), layout files and reference designs are available online at http://www.xilinx.com/products/boards/vc7203 FPGA Compatibility The VC7203 board is provided with Virtex-7 XC7V485T-3 FFG1761E FPGA. The board will also support all device densities (i.e., XC7VX330T, XC7V585T, XC7VX690T, XC7V1500T, and XC7V2000T devices) in the pin-compatible FFG1761, FLG1761, and FHG1761 packages.

  • Page 6: Detailed Description

    VCCO_HR UG957_c1_01_090512 Figure 1-1: VC7203 Board Block Diagram Detailed Description Figure 1-2 shows the VC7203 board described in this user guide. Each numbered feature that is referenced in Figure 1-2 is described in the sections that follow. Caution! The VC7203 board can be damaged by electrostatic discharge (ESD). Follow standard ESD prevention measures when handling the board.
  • Page 7 Detailed Description X-Ref Target - Figure 1-2 UG957_c1_02_100612 Figure 1-2: VC7203 Board Features. Callouts Listed in Table 1-1 Table 1-1: VC7203 Board Feature Descriptions Reference Figure 1-2 Feature Description Callout Designator Virtex-7 XC7V485T-3 FFG1761E FPGA, page 15 Power switch, page 9...

  • Page 8: Power Management

    41 Power Management Board 12V Input Power VC7203 board receives 12V main power through J2 (callout 3, Figure 1-2) using the 12V AC adapter that ships with the board. J2 is a 6-pin (2 x 3), right angle, Mini-Fit connector.

  • Page 9: Power Switch

    ON position, power is applied to the board and green LED DS11 illuminates (callout 15, Figure 1-2). Onboard Power Regulation Figure 1-3 shows the onboard power supply architecture. VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 10 1.8V at 2.6A max UG957_c1_03_100712 Figure 1-3: VC7203 Board Power Supply Block Diagram The VC7203 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instruments to supply the FPGA logic and utility voltages listed in Table 1-2.

  • Page 11: Using External Power Sources

    Each voltage rail for the FPGA logic and GTX transceivers has an associated jack (or jacks) that can be used to provide power from an external source (Table 1-3). The jacks are binding posts that accept standard banana plugs. VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...

  • Page 12: Default Jumper And Switch Positions

    1-2), is provided for use with the TI USB Interface Adapter PMBus pod and associated TI GUI. References More information about the power system components used by the VC7203 board are available from the Texas Instruments digital power website [Ref...

  • Page 13: Active Heatsink Power Connector

    MGTAVCC, MGTAVTT and MGTVCCAUX power rails. It also lists the maximum current rating for each rail supplied by 7 Series GTX modules included with the VC7203 board. Table 1-4: 7 Series GTX Transceiver Power Module...
  • Page 14 Chapter 1: VC7203 Board Features and Operation X-Ref Target - Figure 1-5 UG957_c1_05_100712 Figure 1-5: Active FPGA Heatsink The fan power connections are detailed in Table 1-5: Table 1-5: Fan Power Connections Fan Wire Header Pin Black J121.1 - GND J121.2 - 12V...

  • Page 15: Virtex-7 Fpga

    Detailed Description Virtex-7 FPGA The VC7203 board is populated with the Virtex-7 XC7V485T-3 FFG1761E FPGA at U1 (callout 1, Figure 1-2). For further information on Virtex-7 FPGAs, see DS180, 7 Series FPGAs Overview. FPGA Configuration The FPGA is configured via JTAG using one of the following options: •...
  • Page 16 Chapter 1: VC7203 Board Features and Operation The JTAG chain of the board is illustrated in Figure 1-7. By default only the Virtex-7 FPGA and the System ACE SD controller are part of the chain (J1 jumper OFF). Installing the J1 jumper adds the FMC interfaces as well.

  • Page 17: Prog_B Push Button

    Figure 1-8: Configuration Address DIP Switch (SW8) The switch settings for selecting each address are shown in Table 1-6. Table 1-6: SW8 DIP Switch Configuration Configuration Bitstream ADR2 ADR1 ADR0 Address VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...

  • Page 18: 200 Mhz 2.5V Lvds Oscillator

    200 MHz 2.5V LVDS Oscillator U35 (callout 11, Figure 1-2). The VC7203 board has one 200 MHz 2.5V LVDS oscillator (U35) connected to multi-region clock capable (MRCC) inputs on the FPGA. Table 1-7 lists the FPGA pin connections to the LVDS oscillator.
  • Page 19 Detailed Description interface. The VC7203 board also supplies UTIL_5V0, UTIL_3V3, UTIL_2V5 and VCCO_HR input power to the clock module interface. Table 1-9: SuperClock-2 FPGA I/O Mapping U1 FPGA Pin Net Name J82 Pin CM_LVDS1_P CM_LVDS1_N CM_LVDS2_P CM_LVDS2_N BA12 CM_LVDS3_P BB12...

  • Page 20: User Leds (Active High)

    Chapter 1: VC7203 Board Features and Operation Table 1-9: SuperClock-2 FPGA I/O Mapping (Cont’d) U1 FPGA Pin Net Name J82 Pin CM_CTRL_23 CM_RST User LEDs (Active High) Callout 23, Figure 1-2. DS13 through DS20 are eight active-High LEDs that are connected to user I/O pins on the...

  • Page 21: User Push Buttons (Active High)

    GTX Transceivers and Reference Clocks Callout 4, Figure 1-2. The VC7203 board provides access to all GTX transceiver and reference clock pins on the FPGA as shown in Figure 1-10. The GTX transceivers are grouped into nine sets of four RX-TX lanes.
  • Page 22 Chapter 1: VC7203 Board Features and Operation Note: Figure 1-10 is for reference only and might not reflect the current revision of the board. X-Ref Target - Figure 1-10 QUAD_115 QUAD_114 QUAD_116 QUAD_113 QUAD_117 QUAD_112 QUAD_118 QUAD_111 QUAD_119 UG957_c1_10_100712 Figure 1-10: GTX Quad Locations...
  • Page 23 2,898 115_TX1_P 2,525 115_TX1_N 2,523 115_RX1_P 2,489 115_RX1_N 2,489 115_TX2_P 2,549 115_TX2_N 2,549 115_RX2_P 2,308 115_RX2_N 2,309 115_TX3_P 2,840 115_TX3_N 2,840 115_RX3_P 2,933 115_RX3_N 2,933 116_TX0_P 2,677 116_TX0_N 2,677 VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 24 Chapter 1: VC7203 Board Features and Operation Table 1-13: GTX Transceiver Pins (Cont’d) Trace Length U1 FPGA Pin Net Name Quad Connector (mils) 116_RX0_P 2,667 116_RX0_N 2,668 116_TX1_P 2,469 116_TX1_N 2,469 116_RX1_P 2,207 116_RX1_N 2,207 116_TX2_P 2,359 116_TX2_N 2,357 116_RX2_P...
  • Page 25 1-14. Table 1-14: GTX Transceiver Reference Clock Inputs U1 FPGA Pin Net Name Quad Connector 115_REFCLK0_P 115_REFCLK0_N 115_REFCLK1_P 115_REFCLK1_N 116_REFCLK0_P 116_REFCLK0_N 116_REFCLK1_P 116_REFCLK1_N 117_REFCLK0_P 117_REFCLK0_N 117_REFCLK1_P 117_REFCLK1_N 118_REFCLK0_P 118_REFCLK0_N VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...

  • Page 26: Usb-To-Uart Bridge

    Bidirectional differential serial data (P-side). GROUND Signal ground. The CP2103 supports an IO voltage range of 1.8V to 3.3V. Xilinx UART IP is expected to be implemented in the FPGA fabric. The FPGA supports the USB-to-UART bridge using four signal pins: •...

  • Page 27: Fpga Mezzanine Card Hpc Interface

    Callout 27, 28, and 29, Figure 1-2. The VC7203 board features three high pin count (HPC) connectors as defined by the VITA 57.1 FPGA Mezzanine card (FMC) specification. The FMC HPC connector is a 10 x 40 position socket. See Appendix B, VITA 57.1 FMC Connector Pinouts...
  • Page 28 Chapter 1: VC7203 Board Features and Operation The FMC HPC connectors on the VC7203 board are identified as FMC1 at JA2, FMC2 at JA3 and FMC3 at JA4. The connections for each of these connectors are listed in Table 1-18 Table 1-19, page 32 respectively.
  • Page 29 FMC1_HB02_N AF34 FMC1_HB03_P AG34 FMC1_HB03_N AD36 FMC1_HB04_P AD37 FMC1_HB04_N AC35 FMC1_HB05_P AC36 FMC1_HB05_N AB31 FMC1_HB06_CC_P AB32 FMC1_HB06_CC_N AG36 FMC1_HB07_P AH36 FMC1_HB07_N FMC1_HB08_P AA37 FMC1_HB08_N FMC1_HB09_P AA36 FMC1_HB09_N AB36 FMC1_HB10_P VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 30 Chapter 1: VC7203 Board Features and Operation Table 1-18: VITA 57.1 FMC1 HPC Connections at JA2 (Cont’d) U1 FPGA Pin Net Name FMC Pin AB37 FMC1_HB10_N AA34 FMC1_HB11_P AA35 FMC1_HB11_N AE32 FMC1_HB12_P AE33 FMC1_HB12_N AF31 FMC1_HB13_P AF32 FMC1_HB13_N AE34 FMC1_HB14_P...
  • Page 31 FMC1_LA19_P AN36 FMC1_LA19_N AJ36 FMC1_LA20_P AJ37 FMC1_LA20_N AP36 FMC1_LA21_P AP37 FMC1_LA21_N AK37 FMC1_LA22_P AL37 FMC1_LA22_N AN35 FMC1_LA23_P AP35 FMC1_LA23_N AL36 FMC1_LA24_P AM37 FMC1_LA24_N AG33 FMC1_LA25_P AH33 FMC1_LA25_N AK35 FMC1_LA26_P VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 32 Chapter 1: VC7203 Board Features and Operation Table 1-18: VITA 57.1 FMC1 HPC Connections at JA2 (Cont’d) U1 FPGA Pin Net Name FMC Pin AL35 FMC1_LA26_N AH31 FMC1_LA27_P AJ31 FMC1_LA27_N AH34 FMC1_LA28_P AJ35 FMC1_LA28_N AM34 FMC1_LA29_P AN34 FMC1_LA29_N AM31 FMC1_LA30_P...
  • Page 33 FMC2_HA04_N FMC2_HA05_P FMC2_HA05_N FMC2_HA06_P FMC2_HA06_N FMC2_HA07_P FMC2_HA07_N FMC2_HA08_P FMC2_HA08_N FMC2_HA09_P FMC2_HA09_N FMC2_HA10_P FMC2_HA10_N FMC2_HA11_P FMC2_HA11_N FMC2_HA12_P FMC2_HA12_N FMC2_HA13_P FMC2_HA13_N FMC2_HA14_P FMC2_HA14_N FMC2_HA15_P FMC2_HA15_N FMC2_HA16_P FMC2_HA16_N FMC2_HB00_CC_P FMC2_HB00_CC_N FMC2_HB01_P FMC2_HB01_N VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 34 Chapter 1: VC7203 Board Features and Operation Table 1-19: VITA 57.1 FMC1 HPC Connections at JA3 (Cont’d) U1 FPGA Pin Net Name FMC Pin FMC2_HB02_P FMC2_HB02_N FMC2_HB03_P FMC2_HB03_N FMC2_HB04_P FMC2_HB04_N FMC2_HB05_P FMC2_HB05_N FMC2_HB06_CC_P FMC2_HB06_CC_N FMC2_HB07_P FMC2_HB07_N FMC2_HB08_P FMC2_HB08_N FMC2_HB09_P FMC2_HB09_N...
  • Page 35 FMC2_LA03_N FMC2_LA04_P FMC2_LA04_N FMC2_LA05_P FMC2_LA05_N FMC2_LA06_P FMC2_LA06_N FMC2_LA07_P FMC2_LA07_N FMC2_LA08_P FMC2_LA08_N FMC2_LA09_P FMC2_LA09_N FMC2_LA10_P FMC2_LA10_N FMC2_LA11_P FMC2_LA11_N FMC2_LA12_P FMC2_LA12_N FMC2_LA13_P FMC2_LA13_N FMC2_LA14_P FMC2_LA14_N FMC2_LA15_P FMC2_LA15_N FMC2_LA16_P FMC2_LA16_N FMC2_LA17_CC_P FMC2_LA17_CC_N VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 36 Chapter 1: VC7203 Board Features and Operation Table 1-19: VITA 57.1 FMC1 HPC Connections at JA3 (Cont’d) U1 FPGA Pin Net Name FMC Pin FMC2_LA18_CC_P FMC2_LA18_CC_N FMC2_LA19_P FMC2_LA19_N FMC2_LA20_P FMC2_LA20_N FMC2_LA21_P FMC2_LA21_N FMC2_LA22_P FMC2_LA22_N FMC2_LA23_P FMC2_LA23_N FMC2_LA24_P FMC2_LA24_N FMC2_LA25_P FMC2_LA25_N...
  • Page 37 FMC3_HA04_P AY13 FMC3_HA04_N BB14 FMC3_HA05_P BB13 FMC3_HA05_N AV20 FMC3_HA06_P AW20 FMC3_HA06_N BA17 FMC3_HA07_P BB17 FMC3_HA07_N AY20 FMC3_HA08_P BA20 FMC3_HA08_N BA16 FMC3_HA09_P BB16 FMC3_HA09_N AY19 FMC3_HA10_P BA19 FMC3_HA10_N FMC3_HA11_P FMC3_HA11_N VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 38 Chapter 1: VC7203 Board Features and Operation Table 1-20: VITA 57.1 FMC1 HPC Connections at JA4 (Cont’d) U1 FPGA Pin Net Name FMC Pin FMC3_HA12_P FMC3_HA12_N FMC3_HA13_P FMC3_HA13_N FMC3_HA14_P FMC3_HA14_N FMC3_HA15_P FMC3_HA15_N FMC3_HB00_CC_P FMC3_HB00_CC_N FMC3_HB01_P FMC3_HB01_N FMC3_HB02_P FMC3_HB02_N FMC3_HB03_P FMC3_HB03_N...
  • Page 39 FMC3_LA06_N AK12 FMC3_LA07_P AL12 FMC3_LA07_N AM13 FMC3_LA08_P AN13 FMC3_LA08_N AM12 FMC3_LA09_P AM11 FMC3_LA09_N AN15 FMC3_LA10_P AN14 FMC3_LA10_N AN11 FMC3_LA11_P AP11 FMC3_LA11_N AP12 FMC3_LA12_P AR12 FMC3_LA12_N AR15 FMC3_LA13_P AT15 FMC3_LA13_N VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 40 Chapter 1: VC7203 Board Features and Operation Table 1-20: VITA 57.1 FMC1 HPC Connections at JA4 (Cont’d) U1 FPGA Pin Net Name FMC Pin AT12 FMC3_LA14_P AU12 FMC3_LA14_N AV15 FMC3_LA15_P AV14 FMC3_LA15_N AW15 FMC3_LA16_P AY15 FMC3_LA16_N AT17 FMC3_LA17_CC_P AU17 FMC3_LA17_CC_N...

  • Page 41: Xadc

    U43 (Analog Devices P/N ADP123AUJZ-R7). The output voltage of the regulator VCCADC can be adjusted using the potentiometer R233. In addition, the VC7203 board provides two options for providing the reference voltage for the analog-to-digital converter. Either option can be selected by placing a shunt in one of...
  • Page 42 Chapter 1: VC7203 Board Features and Operation • FMC1 • FMC2 • FMC3 An I C component can be accessed by selecting the appropriate channel through the control register of the MUX as shown in Table 1-21. Table 1-21: C Channel Assignments...

  • Page 43: Appendix A: Default Jumper Settings

    Appendix A Default Jumper Settings Table A-1 lists the jumpers that must be installed on the VC7203 board for proper operation. These jumpers must be installed except where specifically noted in this user guide. Note: Any jumper not listed in Table A-1 should be left open for normal operation.
  • Page 44 Appendix A: Default Jumper Settings www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...

  • Page 45: Appendix B: Vita 57.1 Fmc Connector Pinouts

    HB18_N LA32_P LA33_N HB20_P HB21_N 12P0V DP6_C2M_N HB17_N_CC LA32_N HB20_N 3P3V DP5_C2M_P VIO_B_M2C VADJ VADJ 3P3V DP5_C2M_N VIO_B_M2C VADJ VADJ 3P3V RES0 UG957_ac_01_100712 Figure B-1: FMC HPC Connector Pinout VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 46 Appendix B: VITA 57.1 FMC Connector Pinouts www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...

  • Page 47: Appendix C: Master Ucf Listing

    VC7203 Virtex-7 FPGA GTX Transceiver Characterization Board. Net names in the constraints listed below correlate with net names on the VC7203 board schematic. Users must identify the appropriate pins and replace the net names below with net names in the user RTL.
  • Page 48 LOC = AL31 | IOSTANDARD=LVCMOS18; # Bank FMC1_CLK1_M2C_N LOC = AL32 | IOSTANDARD=LVCMOS18; # Bank FMC1_LA29_P LOC = AM34 | IOSTANDARD=LVCMOS18; # Bank FMC1_LA29_N LOC = AN34 | IOSTANDARD=LVCMOS18; # Bank www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...
  • Page 49 LOC = AD37 | IOSTANDARD=LVCMOS18; # Bank FMC1_HB05_P LOC = AC35 | IOSTANDARD=LVCMOS18; # Bank FMC1_HB05_N LOC = AC36 | IOSTANDARD=LVCMOS18; # Bank FMC1_HB07_P LOC = AG36 | IOSTANDARD=LVCMOS18; # Bank VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 50 LOC = AH40 | IOSTANDARD=LVCMOS18; # Bank IO_L20N_T3_17 LOC = AH41 | IOSTANDARD=LVCMOS18; # Bank IO_L21P_T3_DQS_17 LOC = AL41 | IOSTANDARD=LVCMOS18; # Bank IO_L21N_T3_DQS_17 LOC = AL42 | IOSTANDARD=LVCMOS18; # Bank www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...
  • Page 51 LOC = F41 | IOSTANDARD=LVCMOS18; # Bank IO_L11P_T1_SRCC_19 LOC = J40 | IOSTANDARD=LVCMOS18; # Bank IO_L11N_T1_SRCC_19 LOC = J41 | IOSTANDARD=LVCMOS18; # Bank CLK_DIFF_2_P LOC = K39 | IOSTANDARD=LVCMOS18; # Bank VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 52 LOC = AL19 | IOSTANDARD=LVCMOS18; # Bank FMC3_LA19_N LOC = AM19 | IOSTANDARD=LVCMOS18; # Bank FMC3_LA20_P LOC = AK17 | IOSTANDARD=LVCMOS18; # Bank FMC3_LA20_N LOC = AL17 | IOSTANDARD=LVCMOS18; # Bank www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...
  • Page 53 LOC = AT24 | IOSTANDARD=LVCMOS18; # Bank IO_L17P_T2_33 LOC = AV21 | IOSTANDARD=LVCMOS18; # Bank IO_L17N_T2_33 LOC = AW21 | IOSTANDARD=LVCMOS18; # Bank IO_L18P_T2_33 LOC = AU24 | IOSTANDARD=LVCMOS18; # Bank VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 54 LOC = E32 | IOSTANDARD=LVCMOS18; # Bank FMC2_LA25_N LOC = D32 | IOSTANDARD=LVCMOS18; # Bank FMC2_LA26_P LOC = B32 | IOSTANDARD=LVCMOS18; # Bank FMC2_LA26_N LOC = B33 | IOSTANDARD=LVCMOS18; # Bank www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...
  • Page 55 LOC = N26 | IOSTANDARD=LVCMOS18; # Bank FMC2_HA15_P LOC = N23 | IOSTANDARD=LVCMOS18; # Bank FMC2_HA15_N LOC = N24 | IOSTANDARD=LVCMOS18; # Bank FMC2_HA16_P LOC = M27 | IOSTANDARD=LVCMOS18; # Bank VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 56 LOC = H19 | IOSTANDARD=LVCMOS18; # Bank CLK_DIFF_1_N LOC = G18 | IOSTANDARD=LVCMOS18; # Bank CM_GCLK_P LOC = K19 | IOSTANDARD=LVCMOS18; # Bank CM_GCLK_N LOC = J18 | IOSTANDARD=LVCMOS18; # Bank www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...
  • Page 57 LOC = AY3 ; # Bank 111 111_REFCLK0_P LOC = AW10 ; # Bank 111 111_RX2_N LOC = AY7 ; # Bank 111 111_REFCLK0_N LOC = AW9 ; # Bank 111 VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 58 LOC = AA1 ; # Bank 115 115_REFCLK0_P LOC = Y8 ; # Bank 115 115_RX2_N LOC = AA5 ; # Bank 115 115_REFCLK0_N LOC = Y7 ; # Bank 115 www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...
  • Page 59 LOC = B8 ; # Bank 119 119_TX2_N LOC = C1 ; # Bank 119 119_REFCLK0_P LOC = A10 ; # Bank 119 119_RX2_N LOC = B7 ; # Bank 119 VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...
  • Page 60 LOC = E2 ; # Bank 119 119_RX0_P LOC = D8 ; # Bank 119 119_TX0_N LOC = E1 ; # Bank 119 119_RX0_N LOC = D7 ; # Bank 119 www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...

  • Page 61: Appendix D: Additional Resources

    Topics include design assistance, advisories, and troubleshooting tips: http://www.xilinx.com/support/solcenters.htm Further Resources The most up to date information related to the VC7203 board and its documentation is available on the following websites. The VC7203 Characterization Kit product page: http://www.xilinx.com/products/boards/VC7203...

  • Page 62: References

    Information about the power system components used by the VC7203 board is available from the Texas Instruments digital power website at: http://www.ti.com/ww/en/analog/digital-power/index.html Information about the four 7 Series GTX power supply modules included with the VC7203 Characterization Kit is available from the following vendors: Intersil: http://www.intersil.com/en/applications/computing/xilinx.html...

  • Page 63: Appendix E: Regulatory And Compliance Information

    Safety IEC 60950-1:2005, Information technology equipment – Safety, Part 1: General requirements EN 60950-1:2006, Information technology equipment – Safety, Part 1: General requirements VC7203 GTX Transceiver Characterization Board www.xilinx.com UG957 (v1.0) October 10, 2012...

  • Page 64: Markings

    This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment. This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and 2004/108/EC, Electromagnetic Compatibility (EMC) Directive. www.xilinx.com VC7203 GTX Transceiver Characterization Board UG957 (v1.0) October 10, 2012...

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