Section 2: Board Level Design - Xilinx Virtex-5 RocketIO GTP User Manual

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Section 2: Board Level Design

This section describes general design guidelines when designing systems and boards
where the interconnect exhibits transmission line behavior. This situation occurs when
signals have rise and/or fall times smaller than 2.5 times the flight time from one end of the
interconnection to the other end. These guidelines also apply to all designs with high-
speed transceivers.
These guidelines have been used to create boards that have successfully operated at serial
transmission rates in excess of 10 Gb/s. Although designing for 10 Gb/s operation can
seem excessive when the application calls for slower speeds, it is better to design knowing
that constraints can be relaxed for slower speeds if needed. Other interfaces with
challenging signal integrity demands, such as high-speed memory interfaces, also benefit
from the approach used for 10 Gb/s design.
This section includes the following chapters:
"Design Constraints Overview"
"PCB Materials and Traces"
"Design of Transitions"
"Guidelines and Examples"
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
www.xilinx.com 221