Analog Design Guidelines; Overview; Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

R
GTP-to-Board Interface

Analog Design Guidelines

Overview

In designs with FPGAs that contain GTP transceivers, the overall system performance of a
communication link is highly dependent on the characteristics of the power supply and
clocking design on both endpoints. This chapter discusses guidelines and
recommendations for these topics.
As a prerequisite, the design guidelines outlined in the Virtex-5 PC Board Designers Guide
must be observed to keep the power supply and switching noise on the board to a
minimum. Additionally, it is highly recommended to use Point-of-Load (POL) power
distribution techniques as outlined in:
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=al_point_of_load
Refer to the book EMC and the Printed Circuit Board
sponsored by the IEEE Electromagnetic Compatibility Society for additional guidelines.
Implementation of these guidelines not only improves system margins but is a prerequisite
for compliance to regulations as defined by Federal Communications Commission (FCC)
and the Verband Deutscher Elektrotechniker (VDE) regarding Electromagnetic
Compatibility (EMC), Electromagnetic Interference (EMI), and Radio Frequency
Interference (RFI).

Ports and Attributes

Table 10-1
Table 10-1: Analog Pins
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
defines the analog pins.
Pins
MGTAVCC
MGTAVCCPLL
MGTAVTTRX
MGTAVTTRXC
www.xilinx.com
[Ref 6]
Dir
MGTAVCC is the analog supply for the internal analog
In
circuits of the GTP_DUAL tile.
MGTAVCCPLL is the analog supply for the shared PLL
In and the clock routing and muxing network of the
GTP_DUAL tile.
MGTAVTTRX is the analog supply for the receiver circuits
In
and termination of the GTP_DUAL tile.
MGTAVTTRXC is the analog supply for resistor
In
calibration and standby circuit of the entire device.
Chapter 10
by Mark I. Montrose and
Description
201