Xilinx Virtex-5 RocketIO GTP User Manual page 29

R
Table 1-3: GTP_DUAL Port Summary (Continued)
Port
RXSTATUS0[2:0]
RXSTATUS1[2:0]
RXUSRCLK20
RXUSRCLK21
RXUSRCLK0
RXUSRCLK1
RXVALID0
RXVALID1
TXBUFDIFFCTRL0[2:0]
TXBUFDIFFCTRL1[2:0]
TXBUFSTATUS0[1:0]
TXBUFSTATUS1[1:0]
TXBYPASS8B10B0[1:0]
TXBYPASS8B10B1[1:0]
TXCHARDISPMODE0[1:0]
TXCHARDISPMODE1[1:0]
TXCHARDISPVAL0[1:0]
TXCHARDISPVAL1[1:0]
TXCHARISK0[1:0]
TXCHARISK1[1:0]
TXCOMSTART0
TXCOMSTART1
TXCOMTYPE0
TXCOMTYPE1
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Dir Domain
Shows status of PCI Express or SATA
Out RXUSRCLK2 operations. The decoding depends on
the setting of RX_STATUS_FMT.
Input clock used for the interface
In N/A between the FPGA and the GTP
transceiver.
Input clock used for internal RX logic
In N/A
after the RX FIFO.
Indicates symbol lock and valid data on
Out RXUSRCLK2 RXDATA and RXCHARISK[1:0] for
PCI Express.
Controls the strength of the TX pre-
In Async drivers. Tie this port to the same value
as TXDIFFCTRL.
TX buffer status. Indicates TX buffer
Out TXUSRCLK2
overflow or underflow.
Controls the operation of the TX
In TXUSRCLK2
8B/10B encoder on a per-byte basis.
TXCHARDISPMODE and
TXCHARDISPVAL allow the 8B/10B
disparity of outgoing data to be
controlled when 8B/10B encoding is
In TXUSRCLK2
enabled. When 8B/10B encoding is
disabled, TXCHARDISPMODE is used
to extend the data bus for TX interfaces
whose width is a multiple of 10.
TXCHARDISPVAL and
TXCHARDISPMODE allow the
disparity of outgoing data to be
controlled when 8B/10B encoding is
In TXUSRCLK2
enabled. When 8B/10B encoding is
disabled, TXCHARDISPVAL is used to
extend the data bus for 10- and 20-bit
TX interfaces.
Set High to send TXDATA as an
In TXUSRCLK2
8B/10B K character.
Initiates the transmission of the COM
In TXUSRCLK2 sequence selected by TXCOMTYPE
(SATA only).
Selects the type of COM signal to send
In TXUSRCLK2
(SATA only).
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Description
Ports and Attributes
Section (Page)
TX OOB/Beacon
Signaling (page 119), RX
OOB/Beacon Signaling
(page 130), PCI Express
Receive Detect Support
(page 116)
FPGA RX Interface
(page 183)
FPGA RX Interface
(page 183)
RX OOB/Beacon
Signaling (page 130)
Configurable TX Driver
(page 113)
TX Buffering, Phase
Alignment, and Buffer
Bypass (page 104)
Configurable 8B/10B
Encoder (page 99)
Configurable 8B/10B
Encoder (page 99)
Configurable 8B/10B
Encoder (page 99)
Configurable 8B/10B
Encoder (page 99)
TX OOB/Beacon
Signaling (page 119)
TX OOB/Beacon
Signaling (page 119)
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