Description - Xilinx Virtex-5 RocketIO GTP User Manual

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Table 6-14
Table 6-14: TX PISO Attributes

Description

Equation 6-3
oversampling (OVERSAMPLE_MODE = FALSE). If PLL_TXDIVSEL_COMM_OUT is
greater than 1, PLL_TXDIVSEL_OUT must be set to 1, and vice versa.
PLL_TXDIVSEL_COMM_OUT should be used when both GTP transceivers in the
GTP_DUAL tile use the same TX line rate.
When oversampling is activated, use
See
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
defines the TX PISO attributes.
Attribute
OVERSAMPLE_MODE
PLL_TXDIVSEL_OUT_0
PLL_TXDIVSEL_OUT_1
PLL_TXDIVSEL_COMM_OUT
shows how to calculate the TX line rate when operating without
Tx Line Rate
= --------------------------------------------------------------------------------------------------------------------------------------------------- -
PLL_TXDIVSEL_OUT
Tx Line Rate
= ------------------------------------------------------------------------------------------------------------------------------------------------------------ -
PLL_TXDIVSEL_OUT
"Oversampling," page 143
www.xilinx.com
Description
This shared attribute activates the built-in 5x digital
oversampling circuits in both GTP_DUAL transceivers.
Oversampling must be enabled when running the GTP
transceivers at line rates between 100 Mb/s and 500 Mb/s.
TRUE: Built-in 5x digital oversampling enabled for both
GTP transceivers on the tile
FALSE: Digital oversampling disabled
See "Oversampling," page 143
digital oversampling.
Sets the divider for the TX line rate for the individual GTP
transceiver. If PLL_TXDIVSEL_COMM_OUT is greater
than 1, PLL_TXDIVSEL_OUT must be set to 1, and the TX
line rate is set by PLL_TXDIVSEL_COMM_OUT. The
divider can be set to 1, 2, or 4.
Sets a common line rate divider for both GTP transceivers
in a tile. The common divider should be used whenever
both GTP transceivers in a tile use the same line rate
because it reduces skew between lanes.
PLL_TXDIVSEL_OUT must always be set to 1 when
PLL_TXDIVSEL_COMM_OUT is greater than 1. The
divider can be set to 1, 2, or 4.
×
PLL Clock Rate 2
×
PLL_TXDIVSEL_COMM_OUT
Equation 6-4 to calculate the line rate.
×
PLL Clock Rate 2
×
PLL_TXDIVSEL_COMM_OUT
for more information about oversampling.
Parallel In to Serial Out (PISO)
for more details about 5x
Equation 6-3
Equation 6-4
×
5
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