Clocking; Overview - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 5: Tile Features

Clocking

Overview

For proper high-speed operation, the GTP transceiver requires a high-quality, low-jitter,
reference clock. Because of the shared PMA PLL architecture inside the GTP_DUAL tile,
each reference clock sources both channels. The reference clock is used to produce the PLL
clock, which is divided by one, two, or four to make individual TX and RX serial clocks and
parallel clocks for each GTP transceiver. See
The GTP_DUAL reference clock is provided through the CLKIN port. There are three ways
to drive the CLKIN port (see
•
•
•
Using the dedicated clock routing provides the best possible clock to the GTP_DUAL tiles.
Each GTP_DUAL tile has a pair of dedicated clock pins, represented by IBUFDS
primitives, that can be used to drive the dedicated clock routing. Refer to
"GTP-to-Board Interface," REFCLK Guidelines
This clocking section shows how to select the dedicated clocks for use by one or more
GTP_DUAL tiles. Guidelines for driving these pins on the board are discussed in
Chapter 10, "GTP-to-Board Interface."
When GREFCLK clocking is used for a specific GTP_DUAL tile, the dedicated clock
routing is not used. Instead, the global clock resources of the FPGA are connected to the
shared PMA PLL. GREFCLK clocking is not recommended for most designs because of the
increased jitter introduced by the FPGA clock nets.
68
Figure
Using an external oscillator to drive GTP dedicated clock routing
Using a clock from a neighboring GTP_DUAL tile through GTP dedicated clock
routing
Using a clock from inside the FPGA (GREFCLK)
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"Shared PMA PLL," page 60
5-3):
for IBUFDS details.
Virtex-5 RocketIO GTP Transceiver User Guide
R
for details.
Chapter 10,
UG196 (v1.3) May 25, 2007