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Guidelines and Examples
This chapter discusses high-level PCB guidelines and strategies. Design examples are
provided that show how these guidelines are applied how transitions can be modified to
accommodate specific applications.
Summary of Guidelines
This high-level summary provides a quick reference to some of the guidelines already
covered in previous sections, and also introduces some general strategies when designing
high-speed serial channels.
When defining the stack-up, high-speed stripline layers are kept near the bottom of the
board. If all high-speed traces can be routed on the top and/or the bottom microstrip
layers, there is no need for a stripline layer. Wider traces are preferred and widths of 6 mils
to 12 mils are typical.
Unless there are tight space constraints, the differential trace pairs do not need to be
coupled closely. For example, instead of using a 5 mil width with 5 mil spacing, the same
characteristic trace impedance can be obtained using a 7 mil trace width with 12 mil
spacing.
High-speed differential pairs and transitions must be spread apart on adjacent channels
generously to limit crosstalk, even if the paths become longer. In most cases, they
eventually have to be spread out to match connector pin spacings.
For transitions, large clearances of planes must be provided around and below transitions
to limit excess capacitance. Transitions are spaced apart within the same channel. For
example, differential vias typically are not placed next to DC blocking capacitors or
connectors. However, in some specific cases, performance was acceptable with this
placement.
To further limit excess capacitance in vias, the unused pads on vias should be removed and
the via stub length is kept to a minimum. By routing from the top microstrip to the bottom
microstrip, the via stub can be eliminated. Routing from the top microstrip to the bottom-
most stripline layer results in a negligible via stub. If the lowest layers are not available for
high-speed striplines, other striplines can be used. However, the via stub should be
removed by back-drilling the vias.
Use of minimum spacing and clearance design rules is to be avoided, such as 5 mil pad
clearances. These clearances can be detrimental to performance even at lower multi-gigabit
rates due to the excess capacitance from the tight spacing.
Most transitions shown in this document have 40 fF to 200 fF of excess capacitance. One
exception is a press-fit connector with the PCB pin array having about 500 fF to 800 fF of
excess capacitance using these guidelines, with a via stub less than 10 mils. With smaller
antipads or longer via stubs, the excess capacitance is much greater. Because the
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
www.xilinx.com
Chapter 14
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