Clocking From A Neighbor Gtp_Dual Tile - Xilinx Virtex-5 RocketIO GTP User Manual

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Clocking from a Neighbor GTP_DUAL Tile

The external clock from one GTP_DUAL tile can be used to drive the CLKIN ports of
neighboring tiles. The example in
clock six neighboring tiles. A GTP_DUAL tile shares its clock with its neighbors using the
dedicated clock routing resources. Refer to
Guidelines
Note:
margins for high-speed designs are met:
1.
2.
3.
4.
The maximum number of GTP transceivers that can be sourced by a single clock pin pair is
14. Designs with more than 14 transceivers require the use of multiple external clock pins
to ensure that the rules for controlling jitter are followed. When multiple clock pins are
used, an external buffer can be used to drive them from the same oscillator. The same
oscillator must be used when the GTP transceivers are combined to form a single channel
using channel bonding (see
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
for IBUFDS details.
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
GTP_DUAL Tile
Figure 5-5: Multiple GTP_DUAL Tiles with Shared Reference Clock
The following rules must be observed when sharing a reference clock to ensure that jitter
The number of GTP_DUAL tiles above the sourcing GTP_DUAL tile must not exceed three.
The number of GTP_DUAL tiles below the sourcing GTP_DUAL tile must not exceed three.
The total number of GTP_DUAL tiles sourced by the external clock pin pair
(MGTREFCLKN/MGTREFCLKP) must not exceed seven.
All the GTP_DUAL tiles between the source of the reference clock and a tile using the reference
clock, including the tile with a IBUFDS in use, must be instantiated in the design.
"Configurable Channel Bonding (Lane Deskew)," page
www.xilinx.com
Figure 5-5 uses the clock from one GTP_DUAL tile to
Chapter 10, "GTP-to-Board Interface," REFCLK
CLKIN
CLKIN
CLKIN
IBUFDS
MGTREFCLKP
CLKIN
MGTREFCLKN
CLKIN
CLKIN
CLKIN
UG196_c5_05_110306
Clocking
175).
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