Xilinx Virtex-5 RocketIO GTP User Manual page 165

Table of Contents

Advertisement

R
RX Serial Clock
RX
RX
SIPO
EQ
CDR
PMA
PLL
Divider
From PMA PLL
RX-PMA
Phase alignment can only be used for 10-bit internal datapaths (INTDATAWIDTH = 1).
To use RX phase alignment:
1.
2.
3.
4.
5.
6.
7.
Step 6 requires careful consideration. Normally CDR lock is detected by measuring the
quality of incoming data. Methods for detecting CDR lock include:
When the RX buffer is bypassed, data received from the PMA might be distorted due to
phase differences as it passes to the PCS. This makes it difficult to determine whether bad
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
PMA Parallel Clock
(XCLK)
Comma
Over-
Polarity
Sampling
PRBS
Check
RX Buffer Bypassed
RX-PCS
After phase alignment:
- SIPO parallel clock phase matches RXUSRCLK phase
- No phase difference between XCLK and RXUSRCLK
Figure 7-22: Using Phase Alignment
Set RX_BUFFER_USE to FALSE to bypass the RX buffer (optional).
Set RX_XCLK_SEL to RXUSR.
Source RXUSRCLK and RXUSRCLK2 with the RXRECCLK output. Divide
RXRECCLK by 2 if necessary to provide RXUSRCLK2 (see
182
for details).
Reset the RX datapath using GTPRESET or one of the CDR resets.
Wait for the Shared PMA PLL and any DCM or PLL used for RXUSRCLK2 to lock.
Wait for the CDR to lock and provide a stable RXRECCLK.
Drive RXPMASETPHASE High for 32 RXUSRCLK2 cycles and then deassert it.
Finding known data in the incoming datastream (for example, commas or A1/A2
framing characters). In general, several consecutive known data patterns should be
received without error to indicate a CDR lock.
Using the Loss of Sync State Machine (see
Machine," page
155). If incoming data is 8B/10B encoded and the CDR is locked, the
LOS state machine should move to the SYNC_ACQUIRED state and stay there.
www.xilinx.com
Configurable RX Elastic Buffer and Phase Alignment
10B
Detect
/
&
8B
Align
Loss of Sync
RX Status Control
RX Pipe Control
"Configurable Loss-of-Sync State
PCS Parallel
RX Interface
Clock
Parallel Clock
(RXUSRCLK)
(RXUSRCLK2)
Elastic
Buffer
FPGA
Logic
UG196_c7_33_102306
"FPGA RX Interface," page
165

Advertisement

Table of Contents
loading

Table of Contents