Txoutclk Driving Multiple Transceivers For A 2-Byte Datapath - Xilinx Virtex-5 RocketIO GTP User Manual

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TXOUTCLK Driving Multiple Transceivers for a 2-Byte Datapath

Figure 6-7
frequency must be correct for all GTP transceivers, and they must share the same reference
clock. In
divided clock for TXUSRCLK2.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
PLLLKDET
TXOUTCLK
GTP
TXUSRCLK2
Transceiver
TXUSRCLK
TXDATA (16 or 20 bits)
Figure 6-6: PLL Provides Clocks for a 2-Byte Datapath
shows TXOUTCLK driving multiple GTP user clocks. In this situation, the
Figure 6-7, because the top GTP transceiver uses a two-byte interface, it requires a
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PLL_BASE
CLKOUT0
RST
CLKOUT1
CLKIN
LOCKED
BUFG
FPGA TX Interface
Design in
FPGA
UG196_c6_06_032907
95