Toggling Gsr; Providing Clocks In Simulation; Simulating In Verilog; Defining Gsr/Gts In A Test Bench - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 3: Simulation

Toggling GSR

The GSR signal is a global routing of nets in the design that provide a means of setting or
resetting applicable components in the device during configuration.
The simulation behavior of this signal is modeled using the glbl module in Verilog and the
ROC/ROCBUF components in VHDL.

Providing Clocks In Simulation

In simulation, the clocks inside the PMA are generated using the SIM_PERDIV2 parameter
(ps). Any other clocks driven into the user clock must have the same level of precision, or
TX buffer errors (and RX buffer errors in systems without clock correction) can result.
When generating USRCLK, USRCLK2, or reference clock signals in the testbench, the clock
periods must be related to SIM_PERDIV2 and also be a round number (ps). In some cases,
the simulation a clock rate is slightly different from the clock rate used in the actual design.

Simulating in Verilog

The GSR and global 3-state (GTS) signals are defined in the
$XILINX/verilog/src/glbl.v module. The glbl.v module connects the global
signals to the design, which is why it is necessary to compile this module with the other
design files and load it along with the design.v and testfixture.v files for
simulation.

Defining GSR/GTS in a Test Bench

There are two ways to handle GSR and GTS in a test bench:
1.
2.

Simulating in VHDL

The ROCBUF cell controls the emulated GSR signal in a test bench. This component creates
a buffer for the GSR signal and provides an input port on the buffer to drive GSR. This port
must be declared in the entity list and driven through the test bench.
The VHDL code for this cell, located in EX_ROCBUF.vhd, is listed below:
44
In most cases, GSR and GTS do not need to be defined in the test bench. The glbl.v
file declares the GSR and GTS signals and automatically pulses GSR for 100 ns. This
handling is sufficient for back-end simulations and functional simulations as well.
If GSR or GTS needs to be emulated in the test bench, the following snippet of code
must be added to the testfixture.v file:
assign glbl.GSR = gsr_r;
assign glbl.GTS = gts_r;
initial
begin
gts_r = 1'b0;
gsr_r = 1'b1;
#(16*CLOCKPERIOD);
gsr_r = 1'b0;
end
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.all;
www.xilinx.com Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
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