Appendix C: Low Latency Design - Xilinx Virtex-6 FPGA User Manual

Low Latency Design
This appendix illustrates the latency of the different functional blocks inside the TX and the
RX sections of the GTX transceiver.
RX latencies.
X-Ref Target - Figure C-1
TXUSRCLK
TX FPGA
Data
Serial
Data
RXUSRCLK
RX FPGA
Data
Each functional block has a latency defined as the time difference between the inputs and
the outputs of the specific block. Some blocks in the GTX transceiver can be bypassed,
reducing the latency of the datapath through the transmitter or the receiver. The latency of
the blocks is deterministic with the exception of the RX elastic buffer and the TX buffer.
Bypassing buffers requires the phase alignment procedure. Refer to
page 155
www.BDTIC.com/XILINX
Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Latency TX
First serial bit
transmitted/received
Latency RX
Time
Figure C-1: Latency Definition
and RX Buffer Bypass, page 231
www.xilinx.com
Figure C-1 shows a pictorial definition of the TX and
TX Data
Transceiver
RX Data
for more details.
Appendix C
GTX
Loopback
UG198_aC_01_102910
TX Buffer Bypass,
315