Bypassing The Rx Buffer While Using Built-In Oversampling - Xilinx Virtex-5 RocketIO GTP User Manual

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Bypassing the RX Buffer while Using Built-In Oversampling

If OVERSAMPLE_MODE is TRUE to activate built-in oversampling, the RX buffer is
bypassed without the use of phase alignment. Instead, a shallow buffer inside the
Oversampling block is used to resolve phase differences between RXUSRCLK and
RXRECCLK. See
the Oversampling block.
Figure 7-24
buffer in the Oversampling block resolves any phase differences between RXUSRCLK and
the recovered clock it generates.
RX Serial Clock
RX RX
SIPO
EQ CDR
PMA
PLL
Divider
Oversampling block acts as a shallow buffer:
- Resolves phase differences between the Oversampling
From PMA PLL
block recovered clock and RXUSRCLK
- Cannot resolve frequency differences
RX-PMA
To bypass the RX buffer when OVERSAMPLING_MODE is TRUE:
1.
2.
3.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
"Oversampling," page 143
shows how the RX buffer is bypassed with oversampling enabled. The shallow
PMA Parallel Clock
Over-
Polarity
Sampling
PRBS
Check
RX-PCS
Figure 7-24: Buffer Bypass with Oversampling Enabled
Set RX_BUFFER_USE to FALSE to bypass the RX buffer (optional).
Set RX_XCLK_SEL to "RXUSR".
Source RXUSRCLK and RXUSRCLK2 with the RXRECCLK output. Divide
RXRECCLK by 2 if necessary to provide RXUSRCLK2 (see
182 for details).
www.xilinx.com
Configurable RX Elastic Buffer and Phase Alignment
for information about monitoring the status of
(XCLK)
Comma
10B
Detect
/
&
8B
Align
Loss of Sync
RX Status Control
RX Buffer Bypassed
RX Pipe Control
PCS Parallel RX Interface
Clock Parallel Clock
(RXUSRCLK) (RXUSRCLK2)
Elastic
Buffer
FPGA
Logic
UG196_c7_35_102306
"FPGA RX Interface," page
167