Xilinx Virtex-5 RocketIO GTP User Manual page 45

R
The VHDL code for this test bench, located in EX_ROCBUF_tb.vhd, is listed below:
Further details can be found in the Synthesis and Simulation Design Guide, which can be
downloaded from the Xilinx website at
http://www.xilinx.com/support/sw_manuals/xilinx9/download/
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
entity EX_ROCBUF is
port (
CLOCK, ENABLE, SRP,RESET : in std_logic;
C_OUT: out std_logic_vector (3 downto 0)
);
end EX_ROCBUF;
architecture A of EX_ROCBUF is
signal GSR : std_logic;
signal COUNT : std_logic_vector (3 downto 0);
component ROCBUF
port (
I : in std_logic;
O : out std_logic
);
end component;
begin
U1 : ROCBUF port map (I => SRP, O => GSR);
//dummy process
COUNTER : process (CLOCK, ENABLE, RESET)
begin
....................................
....................................
end process COUNTER;
end A
entity EX_ROCBUF_tb is
end EX_ROCBUF_tb;
architecture behavior of EX_ROCBUF_tb is
declare component EX_ROCBUF
declare signals
begin
EX_ROCBUF_inst: EX_ROCBUF PORT MAP(
CLOCK => CLOCK,
ENABLE => ENABLE,
SRP => SRP,
RESET => RESET,
COUT => COUT
);
Clk_generation: process
Begin
...........................
End process
reset <= '1', '0' after CLK_PERIOD * 30;
SRP <= '1', '0' after CLK_PERIOD * 25;
end
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