Examples; Txoutclk Driving A Gtp Tx In 1-Byte Mode - Xilinx Virtex-5 RocketIO GTP User Manual

R
positive edge of TXUSRCLK2. TXUSRCLK2 is the same rate at TXUSRCLK when
TXDATAWIDTH is 0, and one half the rate of TXUSRCLK when TXDATAWIDTH is 1.
Equation 6-2
TXDATAWIDTH.
There are some rules about the relationships between clocks that must be observed for
TXUSRCLK, TXUSRCLK2, and CLKIN. First, TXUSRCLK and TXUSRCLK2 must be
positive edge aligned, with as little skew as possible between them. As a result, low-skew
clock resources (BUFGs and BUFRs) should be used to drive TXUSRCLK and
TXUSRCLK2. When TXUSRCLK and TXUSRCLK2 have the same frequency, the same
clock resource is used to drive both. When the two clocks have different frequencies,
TXUSRCLK is divided to get TXUSRCLK2. The designer must ensure that the two are
positive edge aligned. The
meet this requirement.
Even though they might run at different frequencies, TXUSRCLK, TXUSRCLK2, and
CLKIN must have the same oscillator as their source. Thus TXUSRCLK and TXUSRCLK2
must be multiplied or divided versions of CLKIN. The GTP transceiver provides access to
CLKIN in two ways: the REFCLKOUT pin (shared by both GTP transceivers in the
GTP_DUAL tile), and the TXOUTCLK pin. The
configurations with each pin.
REFCLKOUT is the same as CLKIN. It is free-running, meaning that it operates even
before the shared PMA PLL is locked. However, because REFCLKOUT uses the CLKIN
rate, it might require multiplication and division to produce the required rates for
TXUSRCLK and TXUSRCLK2.
TXOUTCLK provides a copy of CLKIN already divided to the TXUSRCLK rate, potentially
requiring fewer dividers. However, TXOUTCLK is not free-running: it is only valid after
the shared PMA PLL is locked, and cannot be used when TX phase alignment is turned on
(see

Examples

Figure 6-4
drive the parallel clocks for the TX interface.

TXOUTCLK Driving a GTP TX in 1-Byte Mode

In
(TXDATAWIDTH = 0).
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
shows how to calculate the required rate for TXUSRCLK2 based on
TXUSRCLK2 Rate
TXUSRCLK2 Rate
"Examples"
"TX Buffering, Phase Alignment, and Buffer Bypass," page
through Figure 6-8
Figure 6-4, TXOUTCLK is used to drive TXUSRCLK and TXUSRCLK2 for 1-byte mode
www.xilinx.com
TXUSRCLK (TXDATAWIDTH = 0)
=
TXUSRCLK
(
------------------------------- TXDATAWIDTH = 1
=
2
section shows various clock configurations that
"Examples"
show different ways FPGA clock resources can be used to
FPGA TX Interface
Equation 6-2
)
section shows several clock
102).
93