Receiver Latency; Clock Dependency; Resets - Xilinx RocketIO User Manual

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Receiver Latency

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Clock Dependency

All signals used by the FPGA fabric to interact between user logic and the transceiver
depend on an edge of USRCLK2. These signals all have setup and hold times with respect
to this clock. For specific timing values, see Module 3 of the Virtex-II Pro data sheet. The
timing relationships are further discussed and illustrated in
Transceiver Timing

Resets

There are two reset signals, one each for the transmit and receive sections of each gigabit
transceiver. After the DCM locked signal is asserted, the resets can be asserted. The resets
must be asserted for two USRCLK2 cycles to ensure correct initialization of the FIFOs.
Although both the transmit and receive resets can be attached to the same signal, separate
signals are preferred. This allows the elastic buffer to be cleared in case of an
over/underflow without affecting the ongoing TX transmission. The following example is
an implementation to reset all three data-width transceivers.
VHDL Template
54
Latencies for RX_BUFFER_USE = TRUE
RX_DATA_WIDTH
(Approx. TXUSRCLK Cycles)
1
2
4
If RX elastic buffer is bypassed (RX_BUFFER_USE = FALSE), subtract 18.
Model.
-- Module: gt_reset
-- Description: VHDL submodule
-- reset for GT
--
-- Device: Virtex-II Pro Family
---------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.Numeric_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity gt_reset is
port (
USRCLK2_M : in std_logic;
LOCK : in std_logic;
REFCLK : out std_logic;
DCM_LOCKED: in std_logic;
RST : out std_logic);
end gt_reset;
--
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Chapter 3: Digital Design Considerations
Latency
25.25
25
26.5
Appendix A, RocketIO
UG024 (v1.5) October 16, 2002
RocketIO™ Transceiver User Guide