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Table 7-29
Table 7-29: RX Elastic Buffer and Phase-Alignment Attributes
Attribute
OVERSAMPLE_MODE
(1)
RX_BUFFER_USE_0
(1)
RX_BUFFER_USE_1
RX_XCLK_SEL_0
RX_XCLK_SEL_1
Notes:
1. When the RX buffer is bypassed, 10-bit internal data width is necessary, therefore, INTDATAWIDTH = 1.
Description
Using the RX Buffer
Figure 7-21
the PCS Parallel clock domain (RXUSRCLK) in the RX datapath. This bridging is necessary
because there is no guaranteed phase relationship between the parallel clock from the SIPO
(XCLK) and the parallel clocks from the FPGA logic (RXUSRCLK and RXUSRCLK2).
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
defines the RX elastic buffer and phase-alignment attributes.
Enables built-in 5x digital oversampling. Applies to both transceivers in the GTP_DUAL tile.
TRUE: Built-in 5x oversampling enabled
FALSE: Built-in 5x oversampling disabled
TX_BUFFER_USE must be true when OVERSAMPLE_MODE is TRUE. See
page 143
for the remaining configuration steps required to use oversampling.
Use or bypass the RX elastic buffer.
TRUE: Use the RX elastic buffer (normal mode).
FALSE: Permanently bypass the RX elastic buffer. If OVERSAMPLE_MODE is FALSE, RX
phase alignment must be used whenever the RX buffer is bypassed.
Selects which clock is used to drive the RX parallel clock domain (XCLK).
"RXREC": (default) XCLK domain driven by recovered clock from CDR. When
OVERSAMPLE_MODE is TRUE, the recovered clock is sourced from the Oversampling
block.
"RXUSR": RXUSRCLK port drives RX parallel clock domain. Use this mode when
bypassing the RX buffer.
shows how the RX buffer bridges the PMA Parallel clock domain (XCLK) and
www.xilinx.com
Configurable RX Elastic Buffer and Phase Alignment
Description
"Oversampling,"
163
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