Xilinx Virtex-5 RocketIO GTP User Manual page 299

R
Table D-5: DRP Addresses 10 through 17
Bit
10
SATA_MIN_ SATA_MIN_
0
BURST_1[5] WAKE_1[1]
SATA_MIN_ SATA_MIN_
1
BURST_1[4] WAKE_1[0]
SATA_MIN_
2 Do Not Modify
BURST_1[3]
SATA_MIN_ TRANS_TIME_
3
BURST_1[2] FROM_P2_1[15]
SATA_MIN_ TRANS_TIME_
4
BURST_1[1] FROM_P2_1[14]
SATA_MIN_ TRANS_TIME_
5
BURST_1[0] FROM_P2_1[13]
SATA_MIN_ TRANS_TIME_
6
INIT_1[5] FROM_P2_1[12]
SATA_MIN_ TRANS_TIME_
7
INIT_1[4] FROM_P2_1[11]
SATA_MIN_ TRANS_TIME_
8
INIT_1[3] FROM_P2_1[10]
SATA_MIN_ TRANS_TIME_
9
INIT_1[2] FROM_P2_1[9]
SATA_MIN_ TRANS_TIME_
10
INIT_1[1] FROM_P2_1[8]
SATA_MIN_ TRANS_TIME_
11
INIT_1[0] FROM_P2_1[7]
SATA_MIN_ TRANS_TIME_
12
WAKE_1[5] FROM_P2_1[6]
SATA_MIN_ TRANS_TIME_
13
WAKE_1[4] FROM_P2_1[5]
SATA_MIN_ TRANS_TIME_
14
WAKE_1[3] FROM_P2_1[4]
SATA_MIN_ TRANS_TIME_
15
WAKE_1[2] FROM_P2_1[3]
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
11 12
TRANS_ TRANS_
TIME_FROM TIME_NO
_P2_1[2] N_P2_1[2]
TRANS_ TRANS_
TIME_FROM TIME_NO
_P2_1[1] N_P2_1[1]
TRANS_ TRANS_
TIME_FROM TIME_NO
_P2_1[0] N_P2_1[0]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[15] P2_1[15]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[14] P2_1[14]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[13] P2_1[13]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[12] P2_1[12]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[11] P2_1[11]
TRANS_
TRANS_
TIME_NON_ TIME_TO_
P2_1[10] P2_1[10]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[9] P2_1[9]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[8] P2_1[8]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[7] P2_1[7]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[6] P2_1[6]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[5] P2_1[5]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[4] P2_1[4]
TRANS_ TRANS_
TIME_NON_ TIME_TO_
P2_1[3] P2_1[3]
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Address
13 14 15
TRANS_
TIME_TO_ Do Not Modify
P2_1[2]
TRANS_
TIME_TO_ Do Not Modify
P2_1[1]
TRANS_
TIME_TO_ Do Not Modify
P2_1[0]
TX_
BUFFER_ Do Not Modify
USE_1
Do Not
Do Not Modify
Modify
Do Not
Do Not Modify
Modify
Do Not
Do Not Modify
Modify
Do Not TX_XCLK_
Modify SEL_1
Do Not
Do Not Modify
Modify
Do Not
Do Not Modify
Modify
OOBDETECT_
Do Not
THRESHOLD
Modify
_1[2]
OOBDETECT_
Do Not
THRESHOLD
Modify
_1[1]
OOBDETECT_
Do Not
THRESHOLD
Modify
_1[0]
Do Not
Do Not Modify
Modify
CHAN_BOND
Do Not
_SEQ_2_
Modify
ENABLE_1[4]
CHAN_BOND
Do Not
_SEQ_2_
Modify
ENABLE_1[3]
DRP Address by Bit Location
16 17
CHAN_
CLK_COR_
BOND_SEQ
MAX_LAT_
_2_ENABLE
1[0]
_1[2]
CHAN_
BOND_SEQ CLK_COR_
_2_ENABLE MIN_LAT_1[5]
_1[1]
CHAN_
CLK_COR_
BOND_SEQ
MIN_LAT_1[4]
_2_USE_1
CHAN_
CLK_COR_
BOND_SEQ
MIN_LAT_1[3]
_LEN_1[1]
CHAN_
CLK_COR_
BOND_SEQ
MIN_LAT_1[2]
_LEN_1[0]
CLK_COR_
CLK_COR_MI
ADJ_LEN_
N_LAT_1[1]
1[1]
CLK_COR_
CLK_COR_MI
ADJ_LEN_
N_LAT_1[0]
1[0]
CLK_COR_ CLK_COR_
DET_LEN_ PRECEDENCE
1[1] _1
CLK_COR_ CLK_
DET_LEN_ CORRECT_
1[0] USE_1
CLK_COR_
CLK_COR_
INSERT_
REPEAT_
IDLE_
WAIT_1[4]
FLAG_1
CLK_COR_ CLK_COR_
KEEP_ REPEAT_
IDLE_1 WAIT_1[3]
CLK_COR_ CLK_COR_
MAX_LAT_1 REPEAT_
[5] WAIT_1[2]
CLK_COR_ CLK_COR_
MAX_LAT_1 REPEAT_
[4] WAIT_1[1]
CLK_COR_ CLK_COR_
MAX_LAT_ REPEAT_
1[3] WAIT_1[0]
CLK_COR_
CLK_COR_
MAX_LAT_
SEQ_1_1_1[9]
1[2]
CLK_COR_
CLK_COR_
MAX_LAT_
SEQ_1_1_1[8]
1[1]
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