Xilinx Virtex-5 RocketIO GTP User Manual page 53

R
XC5VLX30T: GTP_DUAL_X0Y3
XC5VLX50T: GTP_DUAL_X0Y4
XC5VSX35T: GTP_DUAL_X0Y3
XC5VSX50T: GTP_DUAL_X0Y3
XC5VLX30T: GTP_DUAL_X0Y2
XC5VLX50T: GTP_DUAL_X0Y3
XC5VSX35T: GTP_DUAL_X0Y2
XC5VSX50T: GTP_DUAL_X0Y2
XC5VLX30T: GTP_DUAL_X0Y1
XC5VLX50T: GTP_DUAL_X0Y2
XC5VSX35T: GTP_DUAL_X0Y1
XC5VSX50T: GTP_DUAL_X0Y1
XC5VLX30T: GTP_DUAL_X0Y0
XC5VLX50T: GTP_DUAL_X0Y1
XC5VSX35T: GTP_DUAL_X0Y0
XC5VSX50T: GTP_DUAL_X0Y0
Figure 4-2: XC5VLX30T-FF665, XC5VLX50T-FF665, XC5VSX35T-FF665, and XC5VSX50T-FF665 GTP Placement
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Right Edge of the Die
D4
D3
F1
E1
C1
D1
G2
F2
B2
C2
K4
K3
M1
L1
J1
K1
N2
M2
H2
J2
T4
T3
V1
U1
R1
T1
W2
V2
P2
R2
AB4
AB3
AD1
AC1
AA1
AB1
AE2
AD2
Y2
AA2
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Package Placement Information
F3
MGTREFCLKP_116
MGTREFCLKN_116
MGTRXP1_116
E3
E4
MGTRXN1_116
MGTRXP0_116
C3
MGTRXN0_116
MGTTXP1_116
B3
G3
MGTTXN1_116
MGTTXP0_116
MGTTXN0_116
M3
MGTREFCLKP_112
MGTREFCLKN_112
MGTRXP1_112
L3
MGTRXN1_112
L4
MGTRXP0_112
J3
MGTRXN0_112
MGTTXP1_112
H3
MGTTXN1_112
N3
MGTTXP0_112
MGTTXN0_112
V3
MGTREFCLKP_114
MGTREFCLKN_114
MGTRXP1_114
U3
MGTRXN1_114
U4
MGTRXP0_114
R3
MGTRXN0_114
MGTTXP1_114
P3
W3
MGTTXN1_114
MGTTXP0_114
MGTTXN0_114
MGTREFCLKP_118
AD3
MGTREFCLKN_118
MGTRXP1_118
AC3
AC4
MGTRXN1_118
MGTRXP0_118
AA3
MGTRXN0_118
MGTTXP1_118
AE3
Y3
MGTTXN1_118
MGTTXP0_118
MGTTXN0_118
Power Pins
MGTAVCCPLL_116
MGTAVCC_116
MGTAVCC_116
MGTAVTTRX_116
MGTAVTTTX_116
MGTAVTTTX_116
MGTAVCCPLL_112
MGTAVCC_112
MGTAVCC_112
MGTAVTTRX_112
MGTAVTTTX_112
MGTAVTTTX_112
MGTAVCCPLL_114
MGTAVCC_114
MGTAVCC_114
MGTAVTTRX_114
MGTAVTTTX_114
MGTAVTTTX_114
MGTAVCCPLL_118
MGTAVCC_118
MGTAVCC_118
MGTAVTTRX_118
MGTAVTTTX_118
MGTAVTTTX_118
UG196_c4_02_012007
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