Xilinx Virtex-5 RocketIO GTP User Manual page 35

R
Table 1-4: GTP_DUAL Attribute Summary (Continued)
Attribute
PLL_DIVSEL_FB
PLL_DIVSEL_REF
PLL_RXDIVSEL_OUT_0
PLL_RXDIVSEL_OUT_1
PLL_SATA_0
PLL_SATA_1
PLL_TXDIVSEL_COMM_OUT
PLL_TXDIVSEL_OUT_0
PLL_TXDIVSEL_OUT_1
PMA_CDR_SCAN_0
PMA_CDR_SCAN_1
PMA_COM_CFG
PMA_RX_CFG_0
PMA_RX_CFG_1
PRBS_ERR_THRESHOLD_0
PRBS_ERR_THRESHOLD_1
RCV_TERM_GND_0
RCV_TERM_GND_1
RCV_TERM_MID_0
RCV_TERM_MID_1
RCV_TERM_VTTRX_0
RCV_TERM_VTTRX_1
RX_BUFFER_USE_0
RX_BUFFER_USE_1
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Description
Controls the feedback divider of the shared
PMA PLL.
Controls the reference clock divider of the
shared PMA PLL.
Defines the nominal line rate for the
receiver based on the shared PMA PLL rate.
Tie to FALSE. When FALSE, allows TX
SATA operations to work at the SATA1 or
SATA2 rate.
Sets a common line rate divider for both
GTP transceivers in a tile. Can be used
instead of PLL_TXDIVSEL_OUT if both
transceivers are using the same TX divider
value.
Sets the divider for the TX line rate for each
GTP transceiver.
Allows direct control of the CDR sampling
point
Common configuration attribute for the
PMA.
Adjusts CDR operation for oversampling
and PLL_RXDIVSEL_OUT settings.
Sets the error threshold for the PRBS
checker.
Sets the RX termination voltage to GND.
Used with internal and external AC
coupling to support PCI Express
TXDETECTRX functionality.
Activates the internal RX termination
voltage. Set to TRUE when RX built-in AC
coupling is used.
Sets RX termination voltage to VTTRX.
Set to TRUE to use the RX elastic buffer.
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Ports and Attributes
Section (Page)
Shared PMA PLL (page 61)
Shared PMA PLL (page 61)
Shared PMA PLL (page 61),
Serial In to Parallel Out (SIPO)
(page 141)
TX OOB/Beacon Signaling
(page 120)
Shared PMA PLL (page 61),
Parallel In to Serial Out (PISO)
(page 111), TX OOB/Beacon
Signaling (page 120)
Shared PMA PLL (page 61),
Parallel In to Serial Out (PISO)
(page 111), TX OOB/Beacon
Signaling (page 120)
RX Clock Data Recovery (CDR)
(page 137)
Marginal Conditions and
Limitations (page 197)
TX Buffering, Phase Alignment,
and Buffer Bypass (page 105)
RX Clock Data Recovery (CDR)
(page 137)
PRBS Detection (page 147)
RX Termination and
Equalization (page 126)
RX Termination and
Equalization (page 126)
RX Termination and
Equalization (page 126)
Configurable RX Elastic Buffer
and Phase Alignment (page 163)
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