Ports And Attributes; Description; Near-End Pcs Loopback - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 9: Loopback
The LOOPBACK[2:0] port selects between the normal operation mode and the different
loopback modes.

Ports and Attributes

Table 9-1
Table 9-1: Loopback Ports
Notes:
1. PCI Express compliant.
Table 9-2: Loopback Attributes

Description

Near-End PCS Loopback

The test data is generated and checked by user logic and then looped back in the PCS. The
difference compared to the Near-End PMA Loopback mode is that the PMA section is not
involved. The test data is looped back before passing the parallel-to-serial and the serial-to-
parallel converter. All analog high-speed circuits in the PMA section can be completely
powered down.
196
defines the Loopback ports.
Port Dir
LOOPBACK0[2:0]
In
LOOPBACK1[2:0]
Attribute
Common PMA configuration attribute. Leave at the default value
PMA_COM_CFG[89:0]
automatically set by the RocketIO GTP Transceiver Wizard.
Figure 9-2
www.xilinx.com
Table 9-2 defines the attributes.
Clock
Domain
000: Normal operation
001: Near-End PCS Loopback
010: Near-End PMA Loopback
011: Reserved
Async
100: Far-End PMA Loopback
101: Reserved
110: Far-End PCS Loopback
111: Reserved
Description
illustrates this configuration.
Virtex-5 RocketIO GTP Transceiver User Guide
Description
(1)
UG196 (v1.3) May 25, 2007
R