Ports And Attributes - Xilinx Virtex-5 RocketIO GTP User Manual

R
The procedures for configuring and using each of the seven major blocks in the
GTP_DUAL tile shown in
1.
2.
3.
4.
5.
6.
7.

Ports and Attributes

This section contains alphabetical tables of pins
(Table
the GTP_DUAL analog pins.
directions, and descriptions for the GTP_DUAL ports.
attribute names, default values, and directions of the GTP_DUAL attributes. In all Port and
Attribute tables in this guide, names that end with 0 are for the GTP0 transceiver on the
tile, and names that end with 1 are for the GTP1 transceiver. Names that do not end with 0
or 1 are shared.
Table 1-2
descriptions.
Table 1-2: GTP_DUAL Analog Pin Summary
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
"Shared PMA PLL," page 60 (Chapter
"Reset," page 72 (Chapter
"Clocking," page 68 (Chapter
"Power Control," page 81 (Chapter
"Dynamic Reconfiguration Port (DRP)," page 87 (Chapter
"GTP Transmitter (TX)," page 89 (Chapter
"GTP Receiver (RX)," page 123 (Chapter
1-4) Table 1-2 lists alphabetically the signal names, directions, and descriptions of
summarizes all GTP_DUAL analog pins and provides links to their detailed
Pin Dir
MGTAVCCPLL In
MGTAVTTRX In
MGTAVTTRXC In
MGTAVTTTX In
MGTAVCC In
MGTREFCLKP
In
MGTREFCLKN
MGTRREF In
www.xilinx.com
Figure 1-2 are discussed in detail in the following sections:
5)
5)
5)
5)
6)
7)
(Table
Table 1-3 lists alphabetically the signal names, clock domains,
Description
Analog supply for the shared
PLL and the clock routing and
muxing network of the
GTP_DUAL tile.
Analog supply for the receiver
circuits and termination of the
GTP_DUAL tile.
Analog supply for resistor
calibration and standby
circuit of the entire device.
Analog supply for the
transmitter termination and
driver circuits of the
GTP_DUAL tile.
Analog supply for the internal
analog circuits of the
GTP_DUAL tile.
Differential clock input pin
pair for the reference clock of
the GTP_DUAL tile.
Reference resistor input for
the entire device.
Ports and Attributes
5)
1-2), ports (Table 1-3), and attributes
Table 1-4 lists alphabetically the
Section (Page)
Analog Design
Guidelines (page 201)
Analog Design
Guidelines (page 201)
Analog Design
Guidelines (page 201)
Analog Design
Guidelines (page 202)
Analog Design
Guidelines (page 201)
Analog Design
Guidelines (page 202)
Analog Design
Guidelines (page 202)
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