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R
Turns add capacitance because the trace at a 90° corner is 41% wider. That difference is
reduced to 8% with a 45° turn. The addition of plane cutouts to a depth of 30 mils act to
reduce this amount of excess capacitance. The trace was not widened to maintain 50Ω with
the plane cutouts in place.
When this mitered bend is simulated with the jog-out and plane cutouts, excess
capacitance is reduced and P/N length and phase matching is improved. Without jog-
outs, the P/N length mismatch is 16 mils. Given FR4 material, the 16 mil difference
translates to a phase mismatch of 4.8° at 5 GHz, or 2.68 ps (0.0268 UI) at 10 Gb/s.
Figure 13-17
outs and 0.3° with jog-outs and plane cutouts. The combination of jog-outs and plane
cutouts yields simulation results that show the excess capacitance of the structure is
reduced to 65 fF.
Designers are tempted to widen lines to compensate for the characteristic impedance
increase as the lines are separated and couple less strongly. However, even without
widening the lines, the combined capacitance of the corners and jog-outs is still overly
capacitive, and therefore the uncoupled section of the jog-out must not be widened.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Two
45°
Turns
Figure 13-16: Example Design for 90 Degree Bends in Traces
through
Figure 13-19
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
0.0
0.2
Figure 13-17: Simulated TDR of 45 Degree Bends with Jog-Outs
www.xilinx.com
Plane
Cut-Outs
show that phase mismatch is reduced to 0.75° with jog-
0.4
0.6
Time, ns
Microstrip/Stripline Bends
Jog-Out
UG196_c13_16_051406
0.8
1.0
UG196_c13_17_051406
247
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