Using The Crc Blocks - Xilinx Virtex-5 RocketIO GTP User Manual

R

Using the CRC Blocks

Figure 8-3
is the CRC32 primitive. This operation is performed when the CRC is being generated or
checked.
In addition to the ports and attributes of the CRC32 primitive,
internal signals, CRC_POLY and CRCINTREG. CRC_POLY is the fixed CRC32 polynomial
used for all calculations. CRCINTREG is an internal register that stores the CRC result after
each cycle of CRC calculation without byte reversal or bit inversion. This value is used
internally, since CRC calculations require the unmanipulated previous cycle CRC result.
First 4 Bytes of the Frame
CRCCLK
CRCRESET
CRCDATAVALID
CRCIN
Don't Care
CRCDATAWIDTH
CRC_INIT
CRC_POLY
CRCINTREG
CRC (Prev Frame)
CRCOUT
f(CRC (Prev Frame))
Notes:
1. Prev = CRCINTREG value from the previous cycle.
2. f(x) = Bit Inverted and Byte Reversed x.
At the start of each frame, CRCRESET must be applied to set the initial CRC value to
CRC_INIT. CRC calculations are cumulative, so this step is required to start the CRC
calculation at a known value. CRC_INIT is a 32-bit value for the initial state of the CRC
internal register. Its default value is 0xFFFFFFFF. The CRC_INIT value required for a
given protocol is specified as part of that protocol's CRC algorithm.
CRC_INIT values for some common protocols that use the CRC32 polynomial.
Table 8-6: CRC_INIT Values for Some Common Protocols
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
shows a CRC block calculating the CRC for input data. Also shown in this figure
D0
3'b011
CRC_INIT CRC (Prev,D0)
f(CRC_INIT) f(CRC(Prev,D0))
Figure 8-3: Normal CRC Operation
Protocol
Ethernet
PCI Express
Infiniband
Fibre Channel
SATA
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Last Word of the Frame -
Only CRCIN[31:24] Valid
D1 D2
32'hFFFFFFFF
32'h04C11DB7
CRC (Prev,D1)
f(CRC(Prev,D1)) f(CRC(Prev,D2))
CRC Result for the Last Valid Data of the
Frame is the CRC Result for the Frame
Figure 8-3 shows two
D3 Don't Care
3'b000 3'b011
CRC (Prev,D2) CRC (Prev,D3)
f(CRC(Prev,D3))
Table 8-6
CRC_INIT
32'hFFFF_FFFF
32'hFFFF_FFFF
32'hFFFF_FFFF
32'hFFFF_FFFF
32'h5232_5032
Description
Next Frame
CRC_INIT
f(CRC_INIT)
UG196_c8_03_100506
shows the
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