Xilinx Virtex-5 RocketIO GTP User Manual page 260

Appendix A: MGT to GTP Transceiver Design Migration
Table A-4: Encoding Support (Continued)
Encoding Schemes Virtex-II Pro MGT
Notes:
1. Encoding and clocks must be done in the FPGA logic.
2. Depending on encode, some functionality must be done in the FPGA logic.
Reference clock multiplication has also evolved over the transceiver generations from a
limited selection of multiplier values to a fully programmable solution starting with
Virtex-4 devices.
devices.
Table A-5: Virtex-II Pro Clock Multipliers
The Virtex-4 and Virtex-5 devices use the circuitry shown in
reference clock.
Table A-6
circuitry as well as the supported divide values. While Virtex-4 devices support separate
multiply ratios for transmit and receive operations, one multiply ratio is used for both in
Virtex-5 devices.
Table A-6: Virtex-4 and Virtex-5 Clock Multiplication Parameters
Divide by M Parameter
Divide by M Values
Divide by N Parameter
Divide by N Values
260
Others
Table A-5
Virtex-II Pro FPGA
Ref Clk
Frequency
Figure A-2: Virtex-4 and Virtex-5 Clock Multiplication Circuitry
shows the parameters used to configure the operation of the clock multiplication
Virtex-4 MGT
TXPLLNDIVSEL, RXPLLNDIVSEL
8, 10, 16, 20, 32, 40
TXOUTDIV2SEL, RXOUTDIV2SEL
1, 2, 4, 8, 16, 32
www.xilinx.com
Virtex-4 MGT
(2)
Yes Yes
shows the clock multiplier values supported in the Virtex-II Pro
Supported Clock Multiplier Values
Phase Charge Pump,
Loop Filter,
Detector VCO
Divide by
M
Divide By M
Parameter
Virtex-5 RocketIO GTP Transceiver User Guide
Virtex-5 GTP Transceiver
(2) (2)
Yes
20
Figure A-2 to multiply the
Divide By N
Parameter
Divide by
Clk Out
N
PLL
UG196_a_02_080606
Virtex-5 GTP Transceiver
PLL_DIVSEL_FB
1, 2, 3, 4, 5
PLL_DIVSEL_REF
1, 2
UG196 (v1.3) May 25, 2007
R