Section 1: Fpga Level Design - Xilinx Virtex-5 RocketIO GTP User Manual

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Section 1: FPGA Level Design

This section provides the information needed to incorporate RocketIO™ GTP transceivers
into an FPGA design, including:
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This section includes the following chapters:
"Introduction to the RocketIO GTP Transceiver"
"RocketIO GTP Transceiver Wizard"
"Simulation"
"Implementation"
"Tile Features"
"GTP Transmitter (TX)"
"GTP Receiver (RX)"
"Cyclic Redundancy Check (CRC)"
"Loopback"
"GTP-to-Board Interface"
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
The features and characteristics of the GTP transceivers
How to use the RocketIO GTP Wizard to configure the transceivers
Mapping of transceiver instances to device resources
Simulation of GTP transceiver designs
Board-level clocking and power requirements
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