Description - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 7: GTP Receiver (RX)

Description

The SIPO block is the heart of the RX datapath. It uses both edges of a high-speed clock to
deserialize incoming data and present it to the PCS.
The serial clock rate to the SIPO, which is the RX line rate of the GTP transceiver, depends
on the PLL clock rate and the setting of PLL_RXDIVSEL_OUT in the GTP transceiver.
Equation 7-2
information on how to set the PLL clock rate.
The parallel clock rate to the parallel side of the SIPO is the XCLK rate of the GTP
transceiver. This rate matches the USERCLK rate of the GTP transceiver, which is used
internally in the PCS. See
for more details about the clock domains in the RX side of the GTP transceiver. The XCLK
rate depends on the internal datapath width used in the tile, because this value is the width
of the parallel data the SIPO produces.
(XCLK) rate of the SIPO.
When OVERSAMPLE_MODE is FALSE, Internal Datapath Width is 8 when
INTDATAWIDTH = 0 and 10 when INTDATAWIDTH = 1. When OVERSAMPLE_MODE
is TRUE, Internal Datapath Width is 10. See
about receiver operation when oversampling is activated.
Both the serial and parallel clocks for the SIPO are generated from the recovered clock in
the CDR circuit.
142
shows how to set the RX line rate. See
RX Line Rate
= ---------------------------------------------------------- -
PLL_RXDIVSEL_OUT
"Configurable RX Elastic Buffer and Phase Alignment," page 161
RX XCLK Rate
= ---------------------------------------------------------------- -
Internal Datapath Width
www.xilinx.com
"Shared PMA PLL," page 60
×
PLL Clock 2
Equation 7-3 shows how to calculate the parallel
RX Line Rate
"Oversampling," page 143
Virtex-5 RocketIO GTP Transceiver User Guide
R
for more
Equation 7-2
Equation 7-3
for more details
UG196 (v1.3) May 25, 2007