Description - Xilinx Virtex-5 RocketIO GTP User Manual

R
Table 6-19: PCI Express Receive Detect Support Ports (Continued)
Port
TXDETECTRX0
TXDETECTRX1
TXPOWERDOWN0[1:0]
TXPOWERDOWN1[1:0]
RXPOWERDOWN0[1:0]
RXPOWERDOWN1[1:0]
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Description

The PCI Express specification includes a feature that allows the transmitter on a given link
to detect if a receiver is present. The decision if a receiver is present is based on the rise time
of TXP/TXN.
transceiver must be in the P1 powerdown state to perform receiver detection. Also receiver
detection requires a 75 to 200 nF external coupling capacitor between the transmitter and
receiver, and the receiver must be terminated to GND.
The detection sequence starts with the assertion of TXDETECTRX. In response, the receive
detect logic drives TXN and TXP to V
programmable interval, the levels of TXN and TXP are compared with a threshold voltage.
At the end of the sequence, RXSTATUS and PHYSTATUS reflect the results of the receiver
detection.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Dir Domain
Activates the receive detection sequence. The sequence ends when
In TXUSRCLK2 PHYSTATUS is asserted to indicate that the results of the test are
ready on RXSTATUS.
Controls the power state of the TX and RX links. The encoding
complies with the PCI Express encoding. TX and RX can be powered
down separately. However, for PCI Express compliance,
TXPOWERDOWN and RXPOWERDOWN must be used together.
In Async
00: P0 (normal operation)
01: P0s (low recovery time powerdown)
10: P1 (longer recovery time/RecDet still on)
11: P2 (lowest power state)
Figure 6-15 shows the circuit model used for receive detection. The GTP
V
DD
R : 40-60Ω
TERMT
TXP
TXDETECTRX
GTP Transceiver
Components
Figure 6-15: Receive Detection Circuit Model
www.xilinx.com
PCI Express Receive Detect Support
Description
– V /2 and then releases them. After a
DD SWING
C : 75-200 nF
AC
C : < 3 nF
CH
Channel
Components
R : 40-60Ω
TERMR
V
TERMR
Far-End Receiver
Components
UG196_c6_15_080806
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