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R
Advanced Clocking
Each GTP_DUAL primitive contains a reference clock multiplexing structure that is
addressable using the DRP port. This structure can connect one out of four different
reference clock sources to the CLKIN port of the GTP_DUAL's shared PLL.
Direct manipulation of the reference clock multiplexers using the DRP port produces
flexible reference clocking arrangements instead of clocking with assignments in HDL. The
reference clock applied to a particular tile can be changed at run-time, provided the PLL is
held in reset using GTPRESET while the change is occurring.
There are several rules to keep in mind when designing a multi-clock scheme:
•
•
•
•
Overlapping clock regions can be constructed when using advanced clocking, a practice
that is not allowed when using HDL to connect the reference clock.
The reference clock multiplexing structure is shown in
MUX are a don't care. Refer to
for IBUFDS details.
Note:
SIM_PLL_PERDIV2 and SIM_GTPRESET_SPEEDUP, for simulating multirate designs.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Only one clock can be forwarded northbound through a tile at a time.
Only one clock can be forwarded southbound through a tile at a time.
A clock cannot be forwarded more than three tiles from its tile of origin in either
direction.
A clock can be forwarded northbound or southbound through a tile, even if the GTP
transceivers in that tile are not using the forwarded clock.
Refer to
Chapter 3, "Simulation"
www.xilinx.com
Figure
Chapter 10, "GTP-to-Board Interface," REFCLK Guidelines
for the correct simulation-only attribute settings,
Appendix F
F-1. The X's in the REFCLK
313
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