Power Control Features For Pci Express - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 5: Tile Features
Table 5-12: TX and RX Power States for Non-PCI Express Operation
TXPOWERDOWN[1:0] or

Power Control Features for PCI Express

The GTP_DUAL tile implements all of the functions needed for power control states
compatible with those defined in the PCI Express and PIPE specifications. When
implementing PCI Express compatible power control, the following conditions must be
met:
•
•
Table 5-13: TX and RX Power States for PCI Express Operation
TXPOWERDOWN[1:0]
and TXDETECTRX
RXPOWERDOWN[1:0]
00 (P0 state)
01 (P0s state)
10 (P1 state)
11 (P2 state)
The GTP transceiver acknowledges changes in the PCI Express power mode by asserting
the PHYSTATUS signal for one clock cycle.
84
RXPOWERDOWN[1:0]
P0 mode. Transceiver TX or RX is active sending or receiving data.
00
P2 mode. Transceiver TX or RX is idle.
11
The TXPOWERDOWN and RXPOWERDOWN on each GTP transceiver must be
connected together to ensure that they are in the same state at all times.
The REFCLKPOWERDNB and PLLPOWERDOWN signals must be held in an
inactive state.
TXELECIDLE
0 0
0 1
1 0
1 1
0
Don't Care
1
Don't Care 0
0 1
1 1
0
Don't Care
1
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Description
Description
The PHY is transmitting data. The MAC provides data
bytes to be sent every clock cycle.
The PHY is not transmitting and is in the electrical idle
state.
The PHY goes into loopback mode.
Not permitted.
The MAC should always put the PHY into the electrical
idle state while in P0s. The PHY behavior is undefined if
TXELECIDLE is deasserted while in P0s or P1.
The PHY is not transmitting and is in the electrical idle
state.
Not permitted. The MAC must always put the PHY into the
electrical idle state while in P1. The PHY behavior is
undefined if TXELECIDLE is deasserted while in P0s or P1.
The PHY is idle.
The PHY does a receiver detection operation.
The PHY transmits beacon signaling
The PHY is idle.
Virtex-5 RocketIO GTP Transceiver User Guide
R
UG196 (v1.3) May 25, 2007