Appendix E: Low Latency Design; Gtp Transmitter Latency - Xilinx Virtex-5 RocketIO GTP User Manual

R
Low Latency Design
This appendix illustrates the latency of the different functional blocks inside the Transmit
and the Receive sections of the GTP transceiver.
Each functional block has a latency defined as the time difference between the inputs and
the outputs of the specific block. Some blocks in the GTP transceiver can be bypassed,
reducing the latency of the datapath through the transmitter or the receiver. The latency of
the blocks is deterministic with the exception of the RX buffer (64-element FIFO) and the
TX buffer (4-element FIFO). Bypassing buffers requires marginal conditions to be met, for
example, phase alignment procedures or USRCLK requirements.
Refer to
Elastic Buffer and Phase Alignment," page
TXUSRCLK2," page
implications and marginal conditions on bypassing buffers.

GTP Transmitter Latency

Figure E-1
"GTP Transmitter (TX),"
GTP transmitter blocks.
9
7
TX
TX TX
OOB
Driver Preemp
&
PCI
8
Shared
PMA
PLL
Divider
From Shared PMA PLL
Table E-1
of the transmitter section of the GTP transceiver. The values in the Block Number column
correspond to the circled numbers in
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
"TX Buffering, Phase Alignment, and Buffer Bypass," page
92, and "Connecting RXUSRCLK and RXUSRCLK2," page 184
shows a detailed block diagram of the GTP transmitter. Refer to
and Figure 6-1, page 89
4
Polarity
Control
PISO
6
TX-PMA TX-PCS
Figure E-1: GTP TX Block Diagram
defines the latency for the specific functional blocks or group of functional blocks
www.xilinx.com
161, "Connecting TXUSRCLK and
for more details on this figure and the
Phase
8B/10B
Adjust
Encoder
FIFO
3
5
PRBS
TX PIPE Control
Generator
Figure E-1.
Appendix E
102, "Configurable RX
for the
Chapter 6,
1
2
FPGA
TX
Interface
UG196_c6_01_042407
309