Xilinx Virtex-5 RocketIO GTP User Manual page 20

Chapter 1: Introduction to the RocketIO GTP Transceiver
Table 1-1: List of Standards Supported by the GTP_DUAL Tile (Continued)
Protocols Supported
10GFC
SDI
HD-SDI
DVB-ASI
10G Base-CX4 802.3ak/D4.0
Gigabit Ethernet (1000BASE-CX
802.3z/D5.0)
SATA Gen 1/II (Rev 1.0a)
SATA Gen. 2 (Rev 1.0a)
SAS Rev 5
Serial RapidIO
CPRI (Ver 2.0)
Infiniband (Volume 2 Release 1.1)
SFI-5
OBSAI RP3 (Spec Issue 1.0)
Aurora
GTP transceivers are placed as dual transceiver GTP_DUAL tiles in Virtex-5 LXT and SXT
Platform devices. This configuration allows two transceivers to share a single PLL with the
TX and RX functions of both, reducing size and power consumption.
Figure 1-1
Additional information on the functional blocks in
locations:
•
•
•
•
20
Protocol Data Rates
Supported
3.1875 Gb/s
143/176/270/360 Mb/s
1.485/1.4835 Gb/s
270 Mb/s
3.125 Gb/s
1.25 Gb/s
1.5 Gb/s
3.0 Gb/s
1.5/3.0 Gb/s
1.25/2.5/3.125 Gb/s
614.4/1228.8/2457.6 Mb/s
2.5 Gb/s
2.488 – 3.125 Gb/s
(1)
768/1536/3072 Mb/s
100 Mb/s – 3.2 Gb/s
shows GTP_DUAL placement in an example Virtex-5 device (XCV5LX110T).
Chapter 8, "Cyclic Redundancy Check (CRC),"
blocks in Figure 1-1.
The Virtex-5 Configuration Guide provides more on the Config and Clock, CMT, and
I/O blocks.
The Virtex-5 Ethernet MAC User Guide provides detailed information on the Ethernet
MAC.
The Virtex-5 Integrated Endpoint Block User Guide for PCI Express Designs provides
detailed information on PCI Express compliance.
www.xilinx.com
Miscellaneous Features
• Rate negotiation for Gen 2 (entire link operates at
Gen 1/Gen 2 speeds)
• LOS
• OOB Beacon
• Synchronous clocking (bypass FIFOs)
Figure 1-1 is available in the following
provides more details on the CRC
Virtex-5 RocketIO GTP Transceiver User Guide
R
UG196 (v1.3) May 25, 2007