Xilinx Virtex-5 RocketIO GTP User Manual page 21

R
I/O
Column
Notes:
1. This figure does NOT illustrate exact size, location or scale of the functional blocks to each other. It does show the correct
number of available resources.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Virtex-5 LX110T
CMT
CMT
CMT
Config
and
Clock
CMT
CMT
CMT
Figure 1-1: GTP_DUAL Inside the Virtex-5 LX110T FPGA
www.xilinx.com
Ethernet
MAC
Ethernet
MAC
I/O
Column
PCI
Express
Overview
GTP_
CRC
DUAL
Blocks
X0_Y7
CRC GTP_
Blocks
DUAL
X0_Y6
GTP_
CRC
DUAL
Blocks
X0_Y5
GTP_
CRC
DUAL
Blocks
X0_Y4
GTP_
CRC
DUAL
Blocks
X0_Y3
GTP_
CRC
DUAL
Blocks
X0_Y2
GTP_
CRC
Blocks DUAL
X0_Y1
CRC GTP_
DUAL
Blocks
X0_Y0
UG196_c1_01_051507
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