Connecting Txusrclk And Txusrclk2 - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 6: GTP Transmitter (TX)
Table 6-2: TX Datapath Width Configuration (Continued)
Figure 6-2
(INTDATAWIDTH = 0) and 8B/10B encoding is disabled.
Figure 6-3
(INTDATAWIDTH = 1) and 8B/10B encoding is disabled. When TXDATA is 10 bits or
20 bits wide, the TXCHARDISPMODE and TXCHARDISPVAL ports are taken from the
8B/10B encoder interface and used to send the extra bits.
Transmitted
Last
TXDATA
TXCHARDISPMODE[1]
TXCHARDIPSVAL[1]
When 8B/10B encoding is used, the data interface is a multiple of 8 bits
the data is encoded before it is transmitted serially.
98

Connecting TXUSRCLK and TXUSRCLK2

The FPGA TX interface includes two parallel clocks: TXUSRCLK and TXUSRCLK2.
TXUSRCLK is the internal clock for the PCS logic in the GTP transmitter. The required rate
for TXUSRCLK depends on the internal datapath width of the GTP_DUAL tile
(INTDATAWIDTH), and the TX line rate of the GTP transmitter
(PISO)," page 110
to calculate the required rate for TXUSRCLK.
TXUSRCLK2 is the main synchronization clock for all signals into the TX side of the GTP
transceiver. Most signals into the TX side of the GTP transceiver are sampled on the
92
INTDATAWIDTH TXDATAWIDTH
1
1
shows how TXDATA is transmitted serially when the internal datapath is 8 bits
Transmitted
Last
TXDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXDATAWIDTH = 1
Figure 6-2: 8B/10B Bypassed, 8-Bit Internal Datapath
shows how TXDATA is transmitted serially when the internal datapath is 10 bits
TXDATAWIDTH = 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TXCHARDISPMODE[0]
TXCHARDIPSVAL[0]
Figure 6-3: 8B/10B Bypassed, 10-Bit Internal Datapath
provides more details about bit ordering when using 8B/10B encoding.
describes how the TX line rate is determined).
TXUSRCLK Rate
www.xilinx.com
TXENC8B10BUSE
1 0
1 1
Transmitted
First
Transmitted Transmitted
First
TXDATA
TXCHARDISPMODE[0]
TXCHARDIPSVAL[0]
"Configurable 8B/10B Encoder," page
Line Rate
= ---------------------------------------------------------------- -
Internal Datapath Width
Virtex-5 RocketIO GTP Transceiver User Guide
FPGA TX Interface Width
20 bits
16 bits
Transmitted Transmitted
Last
TXDATA 7 6 5 4 3 2 1 0
TXDATAWIDTH = 0
UG196_c6_02_051206
TXDATAWIDTH = 0
Transmitted
Last First
7 6 5 4 3 2 1 0
UG196_c6_03_052406
(Figure
("Parallel In to Serial Out
Equation 6-1 shows how
Equation 6-1
UG196 (v1.3) May 25, 2007
R
First
6-2), and