Xilinx Virtex-5 RocketIO GTP User Manual page 298

Appendix D: DRP Address Map of the GTP_DUAL Tile
Table D-4: DRP Addresses 08 through 0F
Bit
08
CHAN_
PCI_EXPRESS
0 BOND_
_MODE_1
SEQ_2_4_1[4]
CHAN_ PCOMMA_
1 BOND_ 10B_VALUE_
SEQ_2_4_1[5]
CHAN_ PCOMMA_
2 BOND_ 10B_VALUE_
SEQ_2_4_1[6]
CHAN_ PCOMMA_
3 BOND_ 10B_VALUE_
SEQ_2_4_1[7]
CHAN_ PCOMMA_
4 BOND_ 10B_VALUE_
SEQ_2_4_1[8]
CHAN_ PCOMMA_
5 BOND_ 10B_VALUE_
SEQ_2_4_1[9]
CHAN_ PCOMMA_
6 BOND_ 10B_VALUE_
SEQ_2_3_1[0]
CHAN_ PCOMMA_
7 BOND_ 10B_VALUE_
SEQ_2_3_1[1]
CHAN_ PCOMMA_
8 BOND_ 10B_VALUE_
SEQ_2_3_1[2]
CHAN_ PCOMMA_
9 BOND_ 10B_VALUE_
SEQ_2_3_1[3]
CHAN_ PCOMMA_
10 BOND_ 10B_VALUE_
SEQ_2_3_1[4]
CHAN_
PCOMMA_
11 BOND_
DETECT_1
SEQ_2_3_1[5]
CHAN_
Do Not
12 BOND_
Modify
SEQ_2_3_1[6]
CHAN_
Do Not
13 BOND_
Modify
SEQ_2_3_1[7]
CHAN_
14 BOND_ PLL_SATA_1
SEQ_2_3_1[8]
Do Not
15 RXDIVSEL_
Modify
OUT_1[1]
298
09 0A
PLL_
PMA_CDR_
RXDIVSEL_
SCAN_1[11]
OUT_1[0]
PMA_CDR_ PMA_CDR_
SCAN_1[26] SCAN_1[10]
1[9]
PMA_CDR_ PMA_CDR_
SCAN_1[25] SCAN_1[9]
1[8]
PMA_CDR_ PMA_CDR_
SCAN_1[24] SCAN_1[8]
1[7]
PMA_CDR_ PMA_CDR_
SCAN_1[23] SCAN_1[7]
1[6]
PMA_CDR_ PMA_CDR_
SCAN_1[22] SCAN_1[6]
1[5]
PMA_CDR_ PMA_CDR_
SCAN_1[21] SCAN_1[5]
1[4]
PMA_CDR_ PMA_CDR_
SCAN_1[20] SCAN_1[4]
1[3]
PMA_CDR_ PMA_CDR_
SCAN_1[19] SCAN_1[3]
1[2]
PMA_CDR_ PMA_CDR_
SCAN_1[18] SCAN_1[2]
1[1]
PMA_CDR_ PMA_CDR_
SCAN_1[17] SCAN_1[1]
1[0]
PMA_CDR_ PMA_CDR_
SCAN_1[16] SCAN_1[0]
PRBS_ERR_
PMA_CDR_
THRESHOLD
SCAN_1[15]
PRBS_ERR_
PMA_CDR_
THRESHOLD
SCAN_1[14]
PRBS_ERR_
PMA_CDR_
THRESHOLD
SCAN_1[13]
PLL_ PRBS_ERR_
PMA_CDR_
THRESHOLD
SCAN_1[12]
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Address
0B 0C
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[27]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[26]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[25]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[24]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[23]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[22]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[21]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[20]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[19]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[18]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[17]
PRBS_ERR_ PRBS_ERR_
THRESHOLD THRESHOLD
_1[16]
PRBS_ERR_
RX_BUFFER_
THRESHOLD
_1[31] _1[15]
PRBS_ERR_ RX_DECODE
THRESHOLD
_1[30] _1[14] MATCH_1
PRBS_ERR_ RX_LOS_
THRESHOLD INVALID_
_1[29] _1[13] INCR_1[2]
PRBS_ERR_ RX_LOS_
THRESHOLD INVALID_
_1[28] _1[12] INCR_1[1]
Virtex-5 RocketIO GTP Transceiver User Guide
0D 0E
RX_LOS_
SATA_MAX_
INVALID_
BURST_1[3]
_1[11] INCR_1[0]
RX_LOSS_OF
SATA_MAX_
_SYNC_
BURST_1[2]
_1[10] FSM_1
RX_LOS_
SATA_MAX_
THRESHOLD
BURST_1[1]
_1[9] _1[2]
RX_LOS_
SATA_MAX_
THRESHOLD
BURST_1[0]
_1[8] _1[1]
RX_LOS_
SATA_MAX_
THRESHOLD
_1[7] _1[0]
RX_SLIDE_ SATA_MAX_
MODE_1
_1[6]
RX_STATUS_ SATA_MAX_
FMT_1
_1[5]
RX_XCLK_ SATA_MAX_
SEL_1
_1[4]
SATA_BURST SATA_MAX_
_VAL_1[2]
_1[3]
SATA_BURST SATA_MAX_
_VAL_1[1]
_1[2]
SATA_BURST SATA_MAX_
_VAL_1[0] WAKE_1[5]
_1[1]
SATA_IDLE_ SATA_MAX_
VAL_1[2] WAKE_1[4]
_1[0]
SATA_IDLE_ SATA_MAX_
USE_1 VAL_1[1] WAKE_1[3]
SATA_IDLE_ SATA_MAX_
_SEQ_
VAL_1[0] WAKE_1[2]
SATA_MAX_ SATA_MAX_
BURST_1[5] WAKE_1[1]
SATA_MAX_ SATA_MAX_
BURST_1[4] WAKE_1[0]
UG196 (v1.3) May 25, 2007
R
0F
INIT_1[5]
INIT_1[4]
INIT_1[3]
INIT_1[2]
INIT_1[1]
INIT_1[0]