Xilinx Virtex-5 RocketIO GTP User Manual page 28

Chapter 1: Introduction to the RocketIO GTP Transceiver
Table 1-3: GTP_DUAL Port Summary (Continued)
Port
RXENSAMPLEALIGN0
RXENSAMPLEALIGN1
RXEQMIX0[1:0]
RXEQMIX1[1:0]
RXEQPOLE0[3:0]
RXEQPOLE1[3:0]
RXLOSSOFSYNC0[1:0]
RXLOSSOFSYNC1[1:0]
RXNOTINTABLE0[1:0]
RXNOTINTABLE1[1:0]
RXOVERSAMPLEERR0
RXOVERSAMPLEERR1
RXPMASETPHASE0
RXPMASETPHASE1
RXPOLARITY0
RXPOLARITY1
RXPOWERDOWN0[1:0]
RXPOWERDOWN1[1:0]
RXPRBSERR0
RXPRBSERR1
RXRECCLK0
RXRECCLK1
RXRESET0
RXRESET1
RXRUNDISP0[1:0]
RXRUNDISP1[1:0]
RXSLIDE0
RXSLIDE1
28
Dir Domain
When High, the 5X oversampler in the
PCS continually adjusts its sample
In RXUSRCLK2 point. When Low, it samples only at the
point that was active before the port
went Low.
Sets the wideband/high-pass mix ratio
In Async
for the RX equalizer.
Sets high-pass filter pole location for
In Async
the RX equalizer.
FPGA status related to byte stream
synchronization, depending on the
Out RXUSRCLK2
state of the RX_LOSS_OF_SYNC_FSM
attribute.
Indicates if RXDATA is the result of an
Out RXUSRCLK2
illegal 8B/10B code and is in error.
Indicates the FIFO in oversampling
Out RXUSRCLK2 circuit has either overflowed or
underflowed.
Aligns the PMA receiver recovered
In RXUSRCLK2 clock with the PCS user clocks,
allowing the RX FIFO to be bypassed.
In RXUSRCLK2 Inverts the polarity of incoming data.
In Async Powers down RX lanes.
Indicates if the number of errors in
PRBS testing exceeds the value set by
Out RXUSRCLK2
the PRBS_ERR_THRESHOLD
attribute.
Recovered clocks derived from the RX
Clock Data Recovery circuit. Clocks the
Out N/A
RX logic between the PMA and the RX
elastic buffer.
In Async Active-High reset for the RX PCS logic.
Shows the running disparity of the
Out RXUSRCLK2 8B/10B encoder when RXDATA is
received.
Implements a comma alignment bump
In RXUSRCLK2 control, allowing manual comma
alignment.
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Description
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
R
Section (Page)
Oversampling
(page 143)
RX Termination and
Equalization (page 125)
RX Termination and
Equalization (page 125)
Configurable Loss-of-
Sync State Machine
(page 155)
Configurable 8B/10B
Decoder (page 157)
Oversampling
(page 143)
Configurable RX Elastic
Buffer and Phase
Alignment (page 162)
RX Polarity Control
(page 146)
Power Control
(page 81), PCI Express
Receive Detect Support
(page 117)
PRBS Detection
(page 147)
FPGA RX Interface
(page 182)
Reset (page 73), FPGA
RX Interface (page 182)
Configurable 8B/10B
Decoder (page 157)
Configurable Comma
Alignment and
Detection (page 150)