Configuring The Shared Pll For - Xilinx Virtex-5 RocketIO GTP User Manual

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Configuring the Shared PLL for OC-48
This example shows how to set the shared PLL divider settings for OC-48 using
Equation
example is provided only to illustrate the process with
Use
1.
2.
3.
4.
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
"Configurable 8B/10B Decoder," page 157
and internal datapath width requirements.
c. Determine the desired reference clock rate.
This example uses a reference clock running at 156.25 MHz, a common rate for
XAUI.
d. Calculate the required PLL clock rate.
Because the Serial-In Parallel-Out (SIPO) block uses both edges of the clock to
deserialize data, it must be fed a clock running at 3.125/2 = 1.5625 GHz. Because
this RX rate of 1.5625 GHz is within the PLL operation range, the external divider
(PLL_RXDIVSEL_OUT) must be one. The PLL clock rate is thus 1.5625 x 1 =
1.5625 GHz.
e. Calculate the required DIV value.
Because the internal datapath with must be 10 bits and INTDATAWIDTH = 1,
DIV = 5.
f. Calculate the required PLL divider ratio.
Using the values f
CLKIN
Equation 5-1 to calculate the divider ratio as shown in
ratio of two.
PLL_DIVSEL_FB
---------------------------------------------------- -
PLL_DIVSEL_REF
g. Select the PLL divider values.
Select the smallest divider values that result in the required PLL divider ratio. In
this case, using PLL_DIVSEL_FB = 2 and PLL_DIVSEL_REF = 1 results in a ratio
of two.
5-1. The RocketIO GTP Wizard and
Equation 5-1 as described in the following steps:
Determine the required line rates.
For OC-48, both TX and RX use a line rate of 2.488 Gb/s.
Determine the internal datapath width.
Because OC-48 uses no encoding and a datapath that is a multiple of eight bits, an
internal datapath width of eight bits is required.
Determine the desired reference clock rate.
This example uses a reference clock running at 155.5 MHz.
Calculate the required PLL clock rate.
Because the SIPO block uses both edges of the clock to deserialize data, it must be fed
a clock running at 2.488/2 = 1.244 GHz. Because this RX rate of 1.244 GHz is within the
operating range of the PLL, the external divider (PLL_RXDIVSEL_OUT) must be one.
The PLL clock rate is thus 1.244 x 1 = 1.244 GHz.
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, DIV, and f determined above, rearrange
PLL_CLOCK
f
1.565 GHz
PLL_Clock
---------------------------------- - ---------------------------------------- -
= =
×
f DIV 156.25 MHz
CLKIN
Table 5-3
Shared PMA PLL
Equation 5-2. The result is a
2
= Equation 5-2
×
5
are simpler alternatives. This
Equation 5-1.
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