Sim_Gtpreset_Speedup; Sim_Pll_Perdiv2 - Xilinx Virtex-5 RocketIO GTP User Manual

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Table 1-4: GTP_DUAL Attribute Summary (Continued)
Attribute
SATA_MIN_WAKE_0
SATA_MIN_WAKE_1

SIM_GTPRESET_SPEEDUP

SIM_PLL_PERDIV2

SIM_RECEIVER_DETECT_PASS0
SIM_RECEIVER_DETECT_PASS1
TERMINATION_CTRL[4:0]
TERMINATION_OVRD
TRANS_TIME_FROM_P2_0
TRANS_TIME_FROM_P2_1
TRANS_TIME_NON_P2_0
TRANS_TIME_NON_P2_1
TRANS_TIME_TO_P2_0
TRANS_TIME_TO_P2_1
TX_BUFFER_USE_0
TX_BUFFER_USE_1
TX_DIFF_BOOST_0
TX_DIFF_BOOST_1
TX_SYNC_FILTERB
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Description
Used to set the minimum time allowed for a
COMWAKE idle for the SATA detector in
terms of squelch clock cycles.
Shortens the time it takes to finish the
GTPRESET sequence and PLL lock during
simulation.
Specifies the length of one symbol in
picoseconds for simulation.
Controls the receiver detect function.
Controls internal termination calibration
circuit.
Selects whether the external 50Ω precision
resistor, connected to the MGTRREF pin, or
an override value is used, as defined by
TERMINATION_CTRL.
Transition time from the P2 powerdown
state in internal 25 MHz clock cycles. The
exact time depends on the CLKIN rate and
the setting of CLK25_DIVIDER.
Transition time to or from any powerdown
state except P2 in internal 25 MHz clock
cycles. The exact time depends on the
CLKIN rate and the setting of
CLK25_DIVIDER.
Transition time to the P2 powerdown state
in internal 25 MHz clock cycles. The exact
time depends on the CLKIN rate and the
setting of CLK25_DIVIDER.
Indicates whether the TX buffer is used.
Changes the strength of the TX driver and
pre-emphasis buffers. When set to TRUE,
the pre-emphasis percentage is boosted or
increased. See Table 6-18, page 114
nominal differential swing and pre-
emphasis values.
Overall differential swing is reduced when
TX_DIFF_BOOST is TRUE.
This parameter must be left at its default
value of 1.
www.xilinx.com
Ports and Attributes
Section (Page)
RX OOB/Beacon Signaling
(page 132)
Simulation (page 42)
Simulation (page 42)
Simulation (page 42)
Analog Design Guidelines,
(page 202)
Analog Design Guidelines,
(page 202)
Power Control (page 82)
Power Control (page 82)
Power Control (page 82)
TX Buffering, Phase Alignment,
and Buffer Bypass
for
Configurable TX Driver
(page 113)
(page 105)
37