Xilinx Virtex-5 RocketIO GTP User Manual page 55

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R
XC5VLX50T: GTP_DUAL_X0Y2
XC5VLX85T: GTP_DUAL_X0Y2
XC5VLX110T: GTP_DUAL_X0Y3
XC5VSX50T: GTP_DUAL_X0Y2
XC5VSX95T: GTP_DUAL_X0Y3
XC5VLX50T: GTP_DUAL_X0Y1
XC5VLX85T: GTP_DUAL_X0Y1
XC5VLX110T: GTP_DUAL_X0Y2
XC5VSX50T: GTP_DUAL_X0Y1
XC5VSX95T: GTP_DUAL_X0Y2
XC5VLX50T: GTP_DUAL_X0Y0
XC5VLX85T: GTP_DUAL_X0Y0
XC5VLX110T: GTP_DUAL_X0Y1
XC5VSX50T: GTP_DUAL_X0Y0
XC5VSX95T: GTP_DUAL_X0Y1
XC5VLX50T: Not Available
XC5VLX85T: Not Available
XC5VLX110T: GTP_DUAL_X0Y0
XC5VSX50T: Not Available
XC5VSX95T: GTP_DUAL_X0Y0
Figure 4-4:
XC5VLX50T-FF1136, XC5VLX85T-FF1136, XC5VLX110T-FF1136, XC5VSX50T-FF1136, and XC5VSX95T-FF1136 GTP Placement (2 of 2)
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Right Edge of the Die
Y4
Y3
AB1
AA1
W1
Y1
AC2
AB2
V2
W2
AF4
AF3
AH1
AG1
AE1
AF1
AJ2
AH2
AD2
AE2
AL5
AL4
AP3
AP2
AL1
AM1
AN4
AN3
AK2
AL2
AL7
AM7
AP9
AP8
AP6
AP7
AN10
AN9
AN5
AN6
www.xilinx.com
Package Placement Information
MGTREFCLKP_114
AB3 MGTAVCCPLL_114
MGTREFCLKN_114
MGTRXP1_114
AA3 MGTAVCC_114
MGTRXN1_114
AA4 MGTAVCC_114
MGTRXP0_114
W3
MGTRXN0_114
MGTTXP1_114
AC3 MGTAVTTTX_114
MGTTXN1_114
V3
MGTTXP0_114
MGTTXN0_114
MGTREFCLKP_118
AH3 MGTAVCCPLL_118
MGTREFCLKN_118
MGTRXP1_118
AG3 MGTAVCC_118
MGTRXN1_118
AG4 MGTAVCC_118
MGTRXP0_118
AE3 MGTAVTTRX_118
MGTRXN0_118
MGTTXP1_118
AD3 MGTAVTTTX_118
MGTTXN1_118
AJ3
MGTTXP0_118
MGTTXN0_118
MGTREFCLKP_122
AM4 MGTAVCCPLL_122
MGTREFCLKN_122
MGTRXP1_122
AJ4
MGTRXN1_122
AK5 MGTAVCC_122
MGTRXP0_122
AL3
MGTRXN0_122
MGTTXP1_122
AK3 MGTAVTTTX_122
MGTTXN1_122
AM3 MGTAVTTTX_122
MGTTXP0_122
MGTTXN0_122
MGTREFCLKP_126
AM9 MGTAVCCPLL_126
MGTREFCLKN_126
MGTRXP1_126
AL8
MGTRXN1_126
AM8 MGTAVCC_126
MGTRXP0_126
AM6 MGTAVTTRX_126
MGTRXN0_126
MGTTXP1_126
AM10 MGTAVTTTX_126
MGTTXN1_126
AM5 MGTAVTTTX_126
MGTTXP0_126
MGTTXN0_126
Power Pins
MGTAVTTRX_114
MGTAVTTTX_114
MGTAVTTTX_118
MGTAVCC_122
MGTAVTTRX_122
MGTAVCC_126
UG196_c4_04_012007
55

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