Ports And Attributes; Description; Clocking From An External Source - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 5: Tile Features

Ports and Attributes

Table 5-4
Table 5-4: Shared Clocking Ports
Table 5-5
Table 5-5: Shared Clocking Attributes

Description

Clocking from an External Source

Each GTP_DUAL tile has a pair of dedicated pins that can be connected to an external
clock source. To use these pins, an IBUFDS primitive is instantiated. In the User
Constraints file, the IBUFDS input pins are constrained to the locations of the dedicated
clock pins for the GTP_DUAL tile. In the design, the output of the IBUFDS is connected to
the CLKIN port. The locations of the dedicated pins for all the GTP_DUAL tiles are
documented in
provides a selection of suitable external oscillators and describes the board-level
requirements for the dedicated reference clock.
pin pair sourced by an external oscillator on the board. Refer to
Interface," REFCLK Guidelines
70
defines the shared clocking ports.
Port Dir
CLKIN In
REFCLKOUT Out
defines the shared clocking attributes.
Attribute
The internal digital logic for GTP_DUAL tile management runs at about
25 MHz. CLK25_DIVIDER is set to get an internal clock for the tile.
1: CLKIN < 25 MHz
2: 25 MHz < CLKIN < 50 MHz
3: 50 MHz < CLKIN < 75 MHz
CLK25_DIVIDER
4: 75 MHz < CLKIN < 100 MHz
5: 100 MHz < CLKIN < 125 MHz
6: 125 MHz < CLKIN < 150 MHz
10: 150 MHz < CLKIN < 250 MHz
12: CLKIN > 250 MHz
Must be set to TRUE. Oscillators driving the dedicated reference clock
CLKINDC_B
inputs must be AC coupled.
Chapter 4, "Implementation." Chapter 10, "GTP-to-Board Interface"
GTP_DUAL
Figure 5-4: Single GTP_DUAL Tile Clocked Externally
www.xilinx.com
Clock Domain
N/A Reference clock input to the shared PMA PLL.
The REFCLKOUT port from each GTP_DUAL
tile provides access to the reference clock
N/A
provided to the shared PLL (CLKIN). It can be
routed for use in the FPGA logic.
Description
Figure 5-4
for IBUFDS details.
IBUFDS
CLKIN
Virtex-5 RocketIO GTP Transceiver User Guide
Description
shows a differential GTP clock
Chapter 10, "GTP-to-Board
MGTREFCLKP
MGTREFCLKN
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