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Clock correction is triggered when the RX elastic buffer latency is too high or too low, and
the clock correction circuit detects a match sequence. To use clock correction, the clock
correction circuit must be configured to set the following items:
•
•
Setting RX Buffer Limits
The RX buffer limits are set using CLK_COR_MIN_LAT (minimum latency) and
CLK_COR_MAX_LAT (maximum latency). When the number of bytes in the RX elastic
buffer drops below CLK_COR_MIN_LAT, the clock correction circuit writes an additional
CLK_COR_ADJ_LEN bytes from the first clock correction sequence it matches to prevent
the buffer from underflowing. Similarly, when the number of bytes in the RX elastic buffer
exceeds CLK_COR_MAX_LAT, the clock correction circuit deletes CLK_COR_ADJ_LEN
bytes from the first clock correction sequence it matches, starting with the first byte of the
sequence.
Setting Clock Correction Sequences
The clock correction sequences are programmed using the CLK_COR_SEQ_1_* attributes
and CLK_COR_ADJ_LEN. Each CLK_COR_SEQ_1_* attribute corresponds to one
subsequence in clock correction sequence 1. CLK_COR_ADJ_LEN is used to set the
number of subsequences to be matched. If INTDATAWIDTH = 1 (10-bit internal datapath),
the clock correction circuit matches all 10 bits of each subsequence. If
INTDATAWIDTH = 0 (8-bit internal datapath), only the right-most eight bits of each
subsequence are used.
A second, alternate clock correction sequence can be activated by setting
CLK_COR_SEQ_2_USE to TRUE. The first and second sequences share length settings, but
use different subsequence values for matching. Set the CLK_COR_SEQ_2_* attributes to
define the subsequence values for the second sequence.
When using 8B/10B decoding (RXDEC8B10BUSE = 1 and INTDATAWIDTH = 1),
RX_DECODE_SEQ_MATCH is set to TRUE to search the output of the 8B/10B decoder for
sequence matches instead of non-decoded data. This allows the circuit to look for 8-bit
values with either positive or negative disparity, and to distinguish K characters from
regular characters (see
8B/10B Decoder," page 157
sequence byte when RX_DECODE_SEQ_MATCH is TRUE.
When RX_DECODE_SEQ_MATCH is FALSE, the sequence must exactly match non-
decoded incoming data. The bit order of the data matches the bit order shown in
Figure 7-34
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
RX buffer limits
Clock correction sequence
"Configurable 8B/10B Encoder," page 98
for details).
and
Figure 7-35
for RXDATA with no 8B/10B decoding.
www.xilinx.com
Configurable Clock Correction
and
Figure 7-26
shows how to set a clock correction
"Configurable
173
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