Xilinx Virtex-5 RocketIO GTP User Manual page 97

R
TXUSRCLK2
TXUSRCLK
GTP
Transceiver
PLLLKDET
GTP_DUAL
REFCLKOUT
Tile
TXUSRCLK2
GTP
Transceiver
TXUSRCLK
Figure 6-8: REFCLKOUT Driving Multiple Transceivers with a 2-Byte Interface
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
TXDATA (16 or 20 bits)
PLL_BASE
RST
CLKIN
BUFG
LOCKED
TXDATA (16 or 20 bits)
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CLKOUT0
CLKOUT1
FPGA TX Interface
Design in
FPGA
UG196_c6_08_040907
97