Xilinx Virtex-5 RocketIO GTP User Manual page 150

Chapter 7: GTP Receiver (RX)
Table 7-20: RX Comma Alignment and Detection Ports (Continued)
Port
RXCOMMADET0
RXCOMMADET1
RXCOMMADETUSE0
RXCOMMADETUSE1
RXENMCOMMAALIGN0
RXENMCOMMAALIGN1
RXENPCOMMAALIGN0
RXENPCOMMAALIGN1
RXSLIDE0
RXSLIDE1
150
Clock
Dir
Domain
This signal is asserted when the comma alignment block detects a
comma. This signal is asserted several cycles before the comma is
available at the FPGA RX interface.
Out RXUSRCLK2
0: Comma not detected
1: Comma detected
RXCOMMADETUSE activates the comma detection and
alignment circuit.
1: Use the comma detection and alignment circuit
In RXUSRCLK2
0: Bypass the circuit
Bypassing the comma and alignment circuit reduces RX datapath
latency.
Aligns the byte boundary when comma minus is detected.
In RXUSRCLK2 0: Disabled
1: Enabled
Aligns the byte boundary when comma plus is detected.
In RXUSRCLK2 0: Disabled
1: Enabled
RXSLIDE implements a comma alignment bump control.
When RXSLIDE is asserted, the byte alignment is adjusted by one
bit, which permits determination and control of byte alignment by
the FPGA logic. Each assertion of RXSLIDE causes just one
In RXUSRCLK2
adjustment.
RXSLIDE must be deasserted for two RXUSRCLK2 cycles before it
can be reasserted to cause another adjustment. When asserted,
RXSLIDE takes precedence over normal comma alignment.
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Description
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
R