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Table 6-1: FPGA TX Interface Ports (Continued)
Port
Dir
TXOUTCLK0
Out
TXOUTCLK1
TXRESET0
In
TXRESET1
TXUSRCLK0
In
TXUSRCLK1
TXUSRCLK20
In
TXUSRCLK21
There are no attributes in this section.
Description
The FPGA TX interface allows parallel data to be written to the GTP transceiver for
transmission as serial data. To use the interface:
•
•
Configuring the Width of the Interface
Table 6-2
is discussed in more detail in
Table 6-2: TX Datapath Width Configuration
Virtex-5 RocketIO GTP Transceiver User Guide
UG196 (v1.3) May 25, 2007
Clock Domain
This port provides a parallel clock generated by the GTP transceiver.
This clock can be used to drive TXUSRCLK for one or more GTP
transceivers. The rate of the clock depends on INTDATAWIDTH:
• INTDATAWIDTH = 0:
N/A
F
• INTDATAWIDTH = 1:
F
When INTDATAWIDTH = 1, the duty cycle is 60/40 instead of 50/50.
Resets the PCS of the GTP transmitter, including the phase adjust
Async
FIFO, the 8B/10B encoder, and the FPGA TX interface.
Use this port to provide a clock for the Internal TX PCS datapath. This
clock must always be provided. The rate depends on
INTDATAWIDTH:
• INTDATAWIDTH = 0:
N/A
F
• INTDATAWIDTH = 1:
F
Use this port to synchronize the FPGA logic with the TX interface.
This clock must be positive-edge aligned to TXUSRCLK. The rate of
this clock depends on F
• TXDATAWIDTH = 0:
N/A
F
• TXDATAWIDTH = 1:
F
The width of the data interface must be configured
TXUSRCLK2 and TXUSRCLK must be connected to clocks running at the correct rate
shows how the interface width for the TX datapath is selected. 8B/10B encoding
INTDATAWIDTH
TXDATAWIDTH
0
0
1
1
www.xilinx.com
Description
= Line Rate/8
TXOUTCLK
= Line Rate/10
TXOUTCLK
= Line Rate/8
TXUSRCLK
= Line Rate/10
TXUSRCLK
TXUSRCLK
= F
TXUSRCLK2
TXUSRCLK
= F
/2
TXUSRCLK2
TXUSRCLK
"Configurable 8B/10B Encoder," page
TXENC8B10BUSE
N/A
0
N/A
1
0
0
0
1
FPGA TX Interface
and TXDATAWIDTH:
98.
FPGA TX Interface Width
8 bits
16 bits
10 bits
8 bits
91
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