Using Rx Phase Alignment - Xilinx Virtex-5 RocketIO GTP User Manual

Chapter 7: GTP Receiver (RX)
RX Serial Clock
RX RX
SIPO
EQ CDR
PMA
PLL
Divider
From PMA PLL
- Resolves phase differences between XCLK and RXUSRCLK
- Resolves frequency differences between XCLK and RXUSRCLK
(requires clock correction)
- Removes RX skew between lanes (requires channel bonding)
RX-PMA
The RX buffer can also be used when OVERSAMPLE_MODE is TRUE.
To use the RX buffer to resolve phase differences between the domains:
•
•
•

Using RX Phase Alignment

The RX buffer can be bypassed to reduce latency when INTDATAWIDTH = 1 (10-bit
internal datapath width) and RXRECCLK is used to source RXUSRCLK and RXUSRCLK2.
When the RX buffer is bypassed, latency through the RX datapath is low and deterministic,
but clock correction and channel bonding are not available.
Figure 7-22
alignment, there is no guaranteed phase relationship between the parallel clock from the
SIPO (XCLK) and the parallel clocks from the FPGA logic (RXUSRCLK and RXUSRCLK2).
Phase alignment causes RXRECCLK from the SIPO to be adjusted so that there is no
significant phase difference between XCLK and RXUSRCLK.
164
PMA Parallel Clock
(XCLK)
Comma
Over-
Polarity
Sampling
PRBS
Check
RX-PCS
Figure 7-21: Using the RX Buffer
Set RX_BUFFER_USE to TRUE.
Reset the buffer whenever RXBUFSTATUS indicates an overflow or an underflow.
The buffer can be reset using GTPRESET (see
RXBUFRESET.
shows how phase alignment allows the RX buffer to be bypassed. Before phase
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10B
Detect
/
&
8B
Align
Loss of Sync
RX Status Control
RX Pipe Control
"Reset," page
Virtex-5 RocketIO GTP Transceiver User Guide
PCS Parallel RX Interface
Clock Parallel Clock
(RXUSRCLK) (RXUSRCLK2)
Elastic
Buffer
FPGA
Logic
UG196_c7_21_102306
72), RXRESET, or
UG196 (v1.3) May 25, 2007
R