Xilinx Virtex-5 RocketIO GTP User Manual page 76

Chapter 5: Tile Features
Figure 5-9
RESETDONE is used in the circuit, TXUSRCLK, TXUSRCLK2, RXUSRCLK, and
RXUSRCLK2 must all be clocked on active GTP transceivers.
Note:
condition occurs, the derived USRCLKs will flatline, because RXRECCLK flatlines when the
generating CDR is in reset. In this case RXELECIDLE(0/1) can be used as a selection signal of a
BUFGMUX to multiplex between the RXRECCLK(0/1) and a different CDR independent clock source.
76
shows the link idle reset circuit required in all GTP designs. Because
GTP_DUAL Tile
RXELECIDLERESET0
RXENELECIDLERESETB
RXELECIDLERESET1
Figure 5-9: Link Idle Reset Implementation
If a RXRECCLK is used to generate or derive any of the USRCLKs and an Electrical Idle
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RESETDONE0
RXELECIDLE0
RESETDONE1
RXELECIDLE1
UG196_c5_09_082806
Virtex-5 RocketIO GTP Transceiver User Guide
R
UG196 (v1.3) May 25, 2007